Clock Slicer User Configurable PECL Output Zero Delay Buffer

MDS 527-03 B

2

Revision 122804

Integrated Circuit Systems, Inc.

Prel iminar y Inf o r m ation

ICS527-03

Pin Assignment

28 pin 150 mil body SSOP

Output Frequency and Output

Divider Table

Pin Descriptions

18

7

17

8

16

9

15

FBPECL

10

FBPECL

11

GND

12

PECL

13

CLKIN

14

PDTS

GND

F6

F0

F5

F3

F1

F4

22

21

20

19

F2

PECL

5

6

S1

VDD

VDD

24

23

R0

3

4

DIV2

S0

R1

26

25

R2

1

2

R5

R6

R3

28

27

R4

RES

S1 S0

Output Divider

Output Frequency (MHz)

0

0

2

10 - 80

01

4

5 - 40

1

0

8

2.5 - 20

1

1

1

20 -160

Pin

Number

Pin

Name

Pin

Type

Pin Description

1,2, 24-28

R5, R6,

R0-R4

Input

Reference divider word input pins determined by user. Forms a binary number

from 0 to 127. Internal pull-up.

3

DIV2

Input

Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based

on the table above. Internal pull-up.

4, 5

S0, S1

Input

Select pins for output divider determined by user. See table above. Internal

pull-up.

6, 23

VDD

Power

Connect to +3.3 V.

7

FPECL

Input

PECL feedback input.

8

FPECL

Input

Complementary PECL feedback input.

9, 20

GND

Power

Connect to ground

10

CLKIN

Input

Clock input.

11

PDTS

Input

Power Down. Active low. Turns off entire chip when low, both clock outputs are

tri-stated. Internal pull-up.

12-18

F0-F6

Input

Feedback divider word input pins determined by user. Forms a binary number

from 0 to 127. Internal pull-up

19

RES

BIAS

Resistor connection to VDD for setting level of PECL outputs.

21

PECL

Output

Complementary PECL input clock.

22

PECL

Output

PECL input clock.