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ICS557-06 Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part # ICS557-06
Description  ONE TO FOUR HCSL CLOCK BUFFER
PDF  10 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS557-06 Datasheet(HTML) 8 Page - Integrated Circuit Systems

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MDS 557-06 C
8
Revision 010306
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
ICS557-06
One to Four HCSL Clock Buffer
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature 0 to +70
°C
1 Test setup is R
L=50 ohms with 2 pF, Rr = 475Ω (1%).
2 Measurement taken from a single-ended waveform.
3 Measurement taken from a differential waveform.
4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5 CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its
PD = low.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
200
MHz
Output Frequency
HCSL termination
200
MHz
LVDS termination
100
Input High Voltage1,2
VIH
HCSL
660
700
850
mV
Input Low Voltage1,2
VIL
HCSL
-150
0
mV
Differential Input
Voltages
(VID)
LVDS
250
350
450
mV
Input Offset Voltage
(VIS)
LVDS
1.125
1.25
1.375
V
Output High Voltage1,2
VOH
HCSL
660
700
850
mV
Output Low Voltage1,2
VOL
HCSL
-150
0
mV
Crossing Point
Voltage1,2
Absolute
250
350
550
mV
Crossing Point
Voltage1,2,4
Variation over all edges
140
mV
Jitter, Cycle-to-Cycle1,3
100
ps
Rise Time1,2
tOR
From 0.175 V to 0.525 V
175
332
700
ps
Fall Time1,2
tOF
From 0.525 V to 0.175 V
175
344
700
ps
Rise/Fall Time
Variation1,2
125
ps
Skew between Outputs
Measured at crossing point
50
ps
Duty Cycle1,3
45
55
%
Output Enable Time5
All outputs
10
us
Output Disable Time5
All outputs
10
us
Stabilization Time
tSTABLE From power-up VDD=3.3 V
3.0
ms
Spread Change Time
tSPREAD Settling period after spread change
3.0
ms
Input to Output Delay
Input differential clock to output
differential clock delay measured at
mid point of input levels to mid pint of
output levels
3ns



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