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ICS8432-101 Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS8432-101 Datasheet(HTML) 9 Page - Integrated Circuit Systems |
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9 / 18 page ![]() 8432DY-101 www.icst.com/products/hiperclocks.html REV. B JUNE 1, 2005 9 Integrated Circuit Systems, Inc. ICS8432-101 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER V CC - 2V 50 Ω 50 Ω RTT Z o = 50Ω Z o = 50Ω FOUT FIN RTT = Z o 1 ((V OH + VOL) / (VCC – 2)) – 2 3.3V 125 Ω 125 Ω 84 Ω 84 Ω Z o = 50Ω Z o = 50Ω FOUT FIN The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are FIGURE 4B. LVPECL OUTPUT TERMINATION FIGURE 4A. LVPECL OUTPUT TERMINATION designed to drive 50 Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be rec- ommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V CC/2 is generated by the bias resistors R1, R2 and C1.This bias circuit should be located as close as possible to the input pin.The ratio FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V CC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. V_REF R1 1K C1 0.1u R2 1K Single Ended Clock Input CLK nCLK VCC |
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