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IMX6SDLIEC Datasheet(PDF) 9 Page - NXP Semiconductors |
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IMX6SDLIEC Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 161 page  Architectural Overview i.MX 6Solo/6DualLite Applications Processors for Industrial Products, Rev. 9, 11/2018 NXP Semiconductors 9 2 Architectural Overview The following subsections provide an architectural overview of the i.MX 6Solo/6DualLite processor system. 2.1 Block Diagram Figure 3 shows the functional modules in the i.MX 6Solo/6DualLite processor system. 1 144 KB RAM including 16 KB RAM inside the CAAM. 2 For i.MX 6Solo, there is only one A9-core platform in the chip; for i.MX 6DualLite, there are two A9-core platforms. Figure 3. i.MX 6Solo/6DualLite System Block Diagram NOTE The numbers in brackets indicate number of module instances. For example, PWM (4) indicates four separate PWM peripherals. Application Processor Smart DMA (SDMA) Shared Peripherals AP Peripherals Arm Cortex-A9 SSI (3) eCSPI (4) MPCore Platform Timers/Control GPT PWM (4) EPIT (2) GPIO WDOG (2) I2C(4) IOMUXC OCTP_CTRL AUDMUX KPP Boot ROM CSU Fuse Box Debug DAP TPIU CAAM (16KB Ram) Security USB OTG + 3 HS Ports CTIs Internal Host PHY2 OTG PHY1 ESAI External Memory I/F RAM (144 KB)1 LDB 1 / 2 LCD Displays Domain (AP) SJC 512K L2 cache SCU, Timer WLAN USB OTG JTAG (IEEE1149.6) Bluetooth MMC/SD eMMC/eSD GPS Audio, Power Mngmnt. SPBA CAN(2) Digital Audio 2xCAN i/f 5xFast-UART SPDIF Rx/Tx Video Proc. Unit (VPU + Cache) 3D Graphics Proc. Unit (GPU3D) 1 / 2 LVDS (WUXGA+) Battery Ctrl Device NOR Flash PSRAM LPDDR2/DDR3 1-Gbps ENET 2x Camera Parallel/MIPI (96KB) PLL (8) CCM GPC SRC XTALOSC OSC32K PTM’s CTI’s HDMI 1.4 Display GPMI HSI/MIPI MIPI Display DSI/MIPI CSI2/MIPI HDMI 2xHSIC PHY PCIe Bus ASRC SNVS (SRTC) uSDHC (4) Modem IC 2D Graphics Proc. Unit (GPU2D) MMC/SD SDXC Raw / ONFI 2.2 NAND Flash MMDC EIM Keypad Crystals & Clock sources Image Processing Subsystem IPUv3H Temp Monitor Mbps 10/100/1000 Ethernet Clock and Reset 400 MHz (DDR800) Power Management Unit (LDOs) 1x/2x A9-Core L1 I/D Cache Timer, WDOG (dev/host) |
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