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IMX6SDLIEC Datasheet(PDF) 1 Page - NXP Semiconductors |
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IMX6SDLIEC Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 161 page ![]() NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6SDLIEC Rev. 9, 11/2018 Package Information Plastic Package BGA Case 2240 21 x 21 mm, 0.8 mm pitch Ordering Information See Table 1 on page 3 NXP Reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products MCIMX6UxCxxxxxB MCIMX6UxCxxxxxC MCIMX6UxCxxxxxD MCIMX6SxCxxxxxB MCIMX6SxCxxxxxC MCIMX6SxCxxxxxD 1 Introduction The i.MX 6Solo/6DualLite processors represent the latest achievement in integrated multimedia-focused products offering high-performance processing with a high degree of functional integration to meet the demands of high-end, advanced industrial and medical applications requiring graphically rich and highly responsive user interfaces. The processors feature advanced implementation of single/dual Arm® Cortex®-A9 core, which operates at speeds of up to 800 MHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 32/64-bit DDR3/DDR3L/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth®, GPS, hard drive, displays, and camera sensors. i.MX 6Solo/6DualLite Applications Processors for Industrial Products 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Updated Signal Naming Convention . . . . . . . . . . . .8 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1 Special Signal Considerations . . . . . . . . . . . . . . . .20 3.2 Recommended Connections for Unused Analog Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .22 4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .22 4.2 Power Supplies Requirements and Restrictions . .32 4.3 Integrated LDO Voltage Regulator Parameters . . .33 4.4 PLL’s Electrical Characteristics . . . . . . . . . . . . . . .35 4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .36 4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .38 4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .42 4.8 Output Buffer Impedance Parameters . . . . . . . . . .46 4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .48 4.10 General-Purpose Media Interface (GPMI) Timing .61 4.11 External Peripheral Interface Parameters . . . . . . .69 5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .127 5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .127 5.2 Boot Device Interface Allocation . . . . . . . . . . . . .128 6 Package Information and Contact Assignments . . . . . .129 6.1 Updated Signal Naming Convention . . . . . . . . . .129 6.2 21x21 mm Package Information. . . . . . . . . . . . . .130 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 |
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