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PCF8536AT Datasheet(PDF) 11 Page - NXP Semiconductors

Part # PCF8536AT
Description  Automotive 36 횞 4 LCD segment driver
PDF  53 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8536AT Datasheet(HTML) 11 Page - NXP Semiconductors

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NXP Semiconductors
PCA8551
Automotive 36 × 4 LCD segment driver
7.3 Starting and resetting the PCA8551
If the internal Power-On Reset (POR) is enabled by connecting pin PORE to VDD, the
chip resets automatically when VDD rises above the minimum supply voltage. No further
action is required.
If the internal POR is disabled by connecting pin PORE to VSS, the chip must be reset by
driving the RST pin (PCA8551A only) to logic 0 for at least 10 μs, see Figure 6.
tw(rst) = 10 µs
minimum
tw(rst) = 10 µs
minimum
VDD(min)
VDD
RST
Valid reset pulse
during power-up
Valid reset pulse
after power-up
aaa-017468
Figure 6. Reset pulse timing
Alternatively a software reset can be applied (see Section 7.3.4).
Following a reset, the register 00h has to be rewritten with 0h by the next command byte
or the address pointer AP[4:0] has to be set to the required address after a new START
procedure. See also application information in Section 15.
7.3.1 Power-down mode
After a reset, the PCA8551 remains in power-down mode. In power-down mode the
oscillator is switched off and there is no output on pin CLK. The register settings remain
unchanged and the bus remains active. To enable the PCA8551, bit DE (command
Display_ctrl_1, see Table 6) must be set to logic 1.
7.3.2 Power-On Reset (POR)
If pin PORE is connected to VDD, the PCA8551 comprises an internal POR, which puts
the device into the following starting conditions:
• All backplane and segment outputs are set to VSS
• The selected drive mode is: 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• The address pointer is cleared (set to logic 0)
• The display and the internal oscillator are disabled
• The display registers are set to logic 0
• The bus interface is initialized
Remark: The internal POR can be disabled by connecting pin PORE to VSS. In this
case, the internal registers are not defined and require a hardware reset according to
Section 7.3.3 or a software reset, see Section 7.3.4.
PCA8551
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 3.1 — 3 May 2021
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