ICS843004AI01 datasheet(1/14 Pages) ICST

Part #	ICS843004AI01

Description	FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

PDF	14 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 14 page

843004AGI-01

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 11, 2005

1

Integrated

Circuit

Systems, Inc.

ICS843004I-01

FEMTOCLOCKS™CRYSTAL-TO-

3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

GENERAL DESCRIPTION

The ICS843004I-01 is a 4 output LVPECL

synthesizer optimized to generate Ethernet

reference clock frequencies and is a member of

the HiPerClocksTM family of high performance clock

solutions from ICS. Using a 25MHz 18pF parallel

resonant crystal, the following frequencies can be generated

based on the settings of 2 frequency select pins (F_SEL[1:0]):

156.25MHz, 125MHz, 62.5MHz. The ICS843004I-01 uses

ICS’ 3rd generation low phase noise VCO technology and can

achieve 1ps or lower typical rms phase jitter, easily meeting

Ethernet jitter requirements. The ICS843004I-01 is packaged

in a small 24-pin TSSOP package.

FEATURES

• Four 3.3V LVPECL outputs

• Selectable crystal oscillator interface

or LVCMOS/LVTTL single-ended input

• Supports the following output frequencies:

156.25MHz, 125MHz and 62.5MHz

• VCO range: 560MHz - 680MHz

• Output skew: 50ps (maximum)

• RMS phase jitter @ 156.25MHz, using a 25MHz crystal

(1.875MHz - 20MHz): 0.54ps (typical)

• Full 3.3V or 2.5V supply modes

• -40°C to 85°C ambient operating temperature

• Lead-Free fully RoHS compliant

HiPerClockS™

ICS

PIN ASSIGNMENT

1

0

1

0

Phase

Detector

VCO

625MHz

(w/25MHz

Reference)

OSC

M = 25 (fixed)

F_SEL[1:0]

0 0 ÷4

0 1 ÷5

1 0 ÷10

1 1 not used

2

ICS843004I-01

24-Lead TSSOP

4.40mm x 7.8mm x 0.92mm

package body

G Package

Top View

nQ1

Q1

VCCo

Q0

nQ0

MR

nPLL_SEL

nc

VCCA

F_SEL0

VCC

F_SEL1

1

2

3

4

5

6

7

8

9

10

11

12

nQ2

Q2

VCCO

Q3

nQ3

VEE

VCC

nXTAL_SEL

TEST_CLK

VEE

XTAL_IN

XTAL_OUT

24

23

22

21

20

19

18

17

16

15

14

13

BLOCK DIAGRAM

s

t

u

p

n

I

y

c

n

e

u

q

e

r

F

t

u

p

t

u

O

)

.

f

e

R

z

H

M

5

2

(

1

L

E

S

_

F0

L

E

S

_

F

r

e

d

i

v

i

D

M

e

u

l

a

V

r

e

d

i

v

i

D

N

e

u

l

a

V

N

/

M

e

u

l

a

V

r

e

d

i

v

i

D

00

5

24

5

2

.

65

2

.

6

5

1

01

5

25

5

2

1

10

5

20

15

.

25

.

2

6

11

5

2d

e

s

u

t

o

nd

e

s

u

t

o

n

FREQUENCY SELECT FUNCTION TABLE

F_SEL[1:0]

nPLL_SEL

TEST_CLK

XTAL_IN

XTAL_OUT

nXTAL_SEL

MR

Q0

nQO

Q1

nQ1

Q2

nQ2

Q3

nQ3

Pulldown

25MHz

Pulldown

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