Networking Clock Synthesizer and Zero Delay Buffer

MDS 680-01 F

2

Revision 020305

Integrated Circuit Systems, Inc.

ICS680-01

Pin Assignment

Output Clock Select Table

Pin Descriptions

13

4

5

CLK1

8

9

10

25M

Q1

QFB

48M

Q2

VDD

17

16

VDD

3

S0

VDD

S1

18

PDTS

1

X1/ICLK

GND

VDD

20

X2

19

14

2

7

GND

GND

ICLK

VDD

15

6

24-pin TSSOP

11

12

GND

Q3

CLK2

Q4

21

22

23

24

S0

S1

CLK1 (MHz)

CLK2 (MHz)

MM

OFF

48

0

0

50

48

0

1

66.6666

48

1

0

50

24

1

1

66.6666

24

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

X1/ICLK

XI

Crystal input. Connect this pin to a crystal or external clock source.

2

GND

Power

Connect to ground.

3

S0

Input

Select pin 0. See table above.

4

VDD

Power

Connect to voltage supply.

5

CLK1

Output

Selectable output clock. See table above. Weak internal pull-down when

tri-state.

6

GND

Power

Connect to ground.

7

GND

Power

Connect to ground.

8

Q1

Output

Clock output 1. Weak internal pull-down when tri-state.

9

Q2

Output

Clock output 2. Weak internal pull-down when tri-state.

10

VDD

Power

Connect to voltage supply.

11

Q3

Output

Clock output 3. Weak internal pull-down when tri-state.

12

Q4

Output

Clock output 4. Weak internal pull-down when tri-state.

13

GND

Power

Connect to ground.

14

CLK2

Output

Selectable output clock. See table above. Weak internal pull-down when

tri-state.

15

48M

Output

48 MHz output clock. Weak internal pull-down when tri-state.

16

VDD

Power

Connect to voltage supply.

17

QFB

Output

Feedback pin. Internally connected.