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ICS680-01 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS680-01 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 8 page ![]() ICS680-01 MDS 680-01 F 1 Revision 020305 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com Networking Clock Synthesizer and Zero Delay Buffer Description The ICS680-01 generates four high-frequency clock outputs and a reference from a 25 MHz crystal or clock input. The device includes a low-skew, single input to four output zero delay clock buffer. It can replace multiple crystals and oscillators, saving board space and cost. The device has a power-down tri-state (PDTS) pin that place the clock outputs in a high-impedance state when pulled low. The PDTS pin includes an internal pull-up resistor. Features • Packaged in 24-pin TSSOP • Available in Pb (lead) free package • Replaces multiple crystals and oscillators • Input crystal or clock frequency of 25 MHz • Five output driver driven by external clock • Duty cycle of 45/55 • Operating voltage of 3.3 V • Advanced, low-power CMOS process • Fixed output frequencies of 25 MHz and 48 MHz • Selectable output frequencies of 24 MHz, 48 MHz, 50 MHz and 66.6666 MHz • Qx outputs replace costly discrete buffer • Low-skew buffer outputs (250 ps) Block Diagram Divide Logic and Output Enable Control External capacitors may be required. S0 VDD CLK2 CLK1 48M 25M Q0 5 Q2 Q3 GND PDTS 2 X1/ICLK X2 Crystal Oscillator 25 MHz Crystal or Clock PLLA PLLB Q1 ICLK S1 PLL/Buffer PLLC QFB |
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