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ICS8547 Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS8547
Description  HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
PDF  12 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS8547 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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ICS8547AY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
1
Integrated
Circuit
Systems, Inc.
HiPerClockS™
,&6
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q4A
nQ4A
nQ4B
Q4B
nCLK4
CLK4
CLK5
nCLK5
Q5B
nQ5B
nQ5A
Q5A
Q2A
nQ2A
nQ2B
Q2B
nCLK2
CLK2
CLK1
nCLK1
Q1B
nQ1B
nQ1A
Q1A
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8547
CLK0
nCLK0
Q0A
nQ0A
Q0B
nQ0B
CLK1
nCLK1
Q1A
nQ1A
Q1B
nQ1B
CLK2
nCLK2
Q2A
nQ2A
Q2B
nQ2B
CLK3
nCLK3
Q3A
nQ3A
Q3B
nQ3B
CLK4
nCLK4
Q4A
nQ4A
Q4B
nQ4B
CLK5
nCLK5
Q5A
nQ5A
Q5B
nQ5B
ICS8547
HEX, LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
GENERAL DESCRIPTION
The ICS8547 is a Hex low skew, high perfor-
mance 1-to-2 Differential-to-LVDS Clock Buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. Utilizing
Low Voltage Differential Signaling (LVDS) the
ICS8547 provides a low power, low noise, point-to-point solu-
tion for distributing clock signals over controlled impedances
of 100
Ω. The ICS8547 has six selectable clock inputs. The
CLKx, nCLKx pairs can accept any differential input levels
and translates them to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew specifications make
the ICS8547 ideal for those applications demanding well
defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
• 12 LVDS outputs
• Selectable CLKx, nCLKx inputs
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS
with resistor bias on nCLKx input
• Output skew: 250ps (maximum)
• Bank skew: 15ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.8ns (maximum)
• 3.3V operating supply
• 0°C to 85°C ambient operating temperature
• Industrial temperature information available upon request


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