LTM4693 datasheet(14/22 Pages) AD

14 / 22 page

LTM4693

Rev. 0

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APPLICATIONS INFORMATION

pertaining to one’s application usage, and can be adapted

to correlate thermal performance to one’s own application.

The Pin Configuration section typically gives three thermal

coefficients explicitly defined in JESD 51-12; these coef-

ficients are quoted or paraphrased below:

1. θJA, the thermal resistance from junction to ambient,

is the natural convection junction-to-ambient air ther-

mal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred

to as “still air” although natural convection causes

the air to move. This value is determined with the

part mounted to a four-layer demo circuit DC3016A.

2. θJCbottom, the thermal resistance from junction to

bottom of the product case, is determined with all of

the component power dissipation flowing through the

bottom of the package. In the typical module regu-

lator, the bulk of the heat flows out the bottom of

the package, but there is always heat flow out into

the ambient environment. As a result, this thermal

resistance value may be useful for comparing pack-

ages but the test conditions don’t generally match the

user’s application.

3. θJCtop, the thermal resistance from junction to top of

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θJCbottom, this value may be useful

for comparing packages but the test conditions don’t

generally match the user’s application.

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 5; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or subgroup of the three thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys nor-

mal operating conditions of a μModule. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bottom

of the µModule—as the standard defines for θJCtop and

θJCbottom, respectively. In practice, power loss is ther-

mally dissipated in both directions away from the pack-

age—granted, in the absence of a heat sink and airflow,

a majority of the heat flow is into the board.

Within the LTM4693 module, be aware there are multiple

power devices and components dissipating power, with

a consequence that the thermal resistances relative to

different junctions of components or die are not exactly

linear with respect to total package power loss. To rec-

oncile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software defined JEDEC environment consistent with

JSED51-12 to predict power loss heat flow and tempera-

ture readings at different interfaces that enable the cal-

culation of the JEDEC-defined thermal resistance values;

(3) the model and FEA software is used to evaluate the

LTM4693 with heat sink and airflow; (4) having solved for

and analyzed these thermal resistance values and simu-

lated various operating conditions in the software model,

a thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled envi-

ronment chamber while operating the device at the same

power loss as simulated. An outcome of this process and

due-diligence yields a set of derating curves shown in

this data sheet.

After these laboratory test have been performed and

correlated to LTM4693 model, then the θJA is provided

assuming approximately 100% of the power loss flows

from the junction through the board into ambient with no

airflow or top mounted heat sink.

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