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ADC3641 Datasheet(PDF) 58 Page - Texas Instruments |
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ADC3641 Datasheet(HTML) 58 Page - Texas Instruments |
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58 / 77 page ![]() Figure 8-61. Register 0x26 7 6 5 4 3 2 1 0 MIX GAIN A MIX RES A FS/4 MIX A MIX GAIN B MIX RES B FS/4 MIX B R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 8-34. Register 0x26 Field Descriptions Bit Field Type Reset Description 7-6 MIX GAIN A R/W 00 This bit applies a 0, 3 or 6-dB digital gain to the output of digital mixer to compensate for the mixing loss for channel A. 00: no digital gain added 01: 3-dB digital gain added 10: 6-dB digital gain added 11: not used 5 MIX RES A R/W 0 Toggling this bit resets the NCO phase of channel A and loads the new NCO frequency. This bit does not self reset. 4 FS/4 MIX A R/W 0 Enables FS/4 mixing for DDC A (complex decimation only). 0: FS/4 mixing disabled. 1: FS/4 mixing enabled. 3-2 MIX GAIN B R/W 00 This bit applies a 0, 3 or 6-dB digital gain to the output of digital mixer to compensate for the mixing loss for channel B. 00: no digital gain added 01: 3-dB digital gain added 10: 6-dB digital gain added 11: not used 1 MIX RES B R/W 0 Toggling this bit resets the NCO phase of channel B and loads the new NCO frequency. This bit does not self reset. 0 FS/4 MIX B R/W 0 Enables FS/4 mixing for DDC B (complex decimation only). 0: FS/4 mixing disabled. 1: FS/4 mixing enabled. Figure 8-62. Register 0x27 7 6 5 4 3 2 1 0 0 0 0 OP ORDER A Q-DEL A FS/4 MIX PH A 0 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 8-35. Register 0x27 Field Descriptions Bit Field Type Reset Description 7-5 0 R/W 0 Must write 0 4 OP ORDER A R/W 0 Swaps the I and Q output order for channel A. See Table 8-36 for recommended settings. Only used with complex decimation. Set to 0 with real decimation. 0: Output order is I[n], Q[n] 1: Output order is swapped: Q[n], I[n] 3 Q-DEL A R/W 0 This delays the Q-sample output of channel A by one. See Table 8-36 for recommended settings. Only used with complex decimation. Set to 0 with real decimation. 0: Output order is I[n], Q[n] 1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2] 2 FS/4 MIX PH A R/W 0 Inverts the mixer phase for channel A when using FS/4 mixer 0: Mixer phase is non-inverted 1: Mixer phase is inverted 1-0 0 R/W 0 Must write 0 ADC3643 SBAS886 – OCTOBER 2020 www.ti.com 58 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: ADC3643 |
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