MAXREFDES43# ZedBoard Quick Start Guide

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8. Appendix B: Code Snippets of Importants

The ‘C’ code provided in this demo does not include precautions such as placing any

authentication code in a TrustZone or bootable area where the code can never change

by hacker intervention. See the Xilinx’s UG1019 found here for more details:

www.xilinx.com/support/documentation/user_guides/ug1019-zynq-trustzone.pdf

9. Appendix C: Pre-Install Master Secret into Bitstream

Background: The DS28C22 ZedBoard Reference Design contains a block RAM in the

ZC7020 FPGA fabric. It is memory mapped at address 0x82cd0000. It is intended to be

used a location to store the master secret for the reference design. This section

describes how to merge a new master secret into the design bitstream. Note: In your

design, it is best to change the memory-mapped address so a hacker will not know the

actual location in memory.

Bitstream: The output of the Xilinx ISE tools will generate a bitstream (top.bit) that

configures all programmable logic inside the FPGA fabric, including block memories.

The default block RAM configuration will have the data at all memory addresses set to

zero. This Block RAM can be initialized to any set of values by using a Xilinx command

line tool called data2mem to merge an existing bitstream with a text file (test.mem) that

contains the desired block memory contents.

Test.mem: The test.mem file alternates memory locations followed by the data for that

memory location. An example configuration is shown below. Each line should contain a

carriage return, and the file does not contain any headers, footers, or checksums.

@82cd0000

3378D863

@82cd0004

0537C88A

@82cd0008

4F57FA55

@82cd000C

98E81450

@82cd0010

AF66F5C5

@82cd0014

20F79E58

@82cd0018

E589FF3A

@82cd001C

758DB5B7