YAC520

4

s Pin Functions

• Power supply pins

Power supply pins

Power supply pins

Power supply pins

AVDD

AVDD

AVDD

AVDD

––––

Analog power supply (+5.0 V)

AVSS

AVSS

AVSS

AVSS

––––

Analog ground

DVDD

DVDD

DVDD

DVDD

––––

Digital power supply (+5.0 V)

DVSS

DVSS

DVSS

DVSS

––––

Digital ground

• Analog Pins

Analog Pins

Analog Pins

Analog Pins

LIN1

LIN1

LIN1

LIN1

––––

Left Channel Analog input 1

Lch analog input pin 1

Gain setting ranges from +32 dB to – 95 dB when the signal inputted to LIN2 is inputted this pin, and

gain setting ranges from +20.0 dB to – 107.0 dB when it is grounded through a capacitor.

LIN2

LIN2

LIN2

LIN2

––––

Left Channel Analog input 2

Lch analog input pin 2

Gain setting ranges from +32 dB to – 95 dB when the signal inputted to LIN1 is inputted this pin, and

gain setting ranges from +29.5 dB to – 97.5 dB when it is grounded through a capacitor.

RIN1

RIN1

RIN1

RIN1

––––

Right Channel Analog input 1

Rch analog input pin 1

Gain setting ranges from +32 dB to – 95 dB when the signal inputted to RIN2 is inputted this pin, and

gain setting ranges from +20.0 dB to – 107.0 dB when it is grounded through a capacitor.

RIN2

RIN2

RIN2

RIN2

––––

Right Channel Analog input 2

Rch analog input pin 2

Gain setting ranges from +32 dB to – 95 dB when the signal inputted to RIN1 is inputted this pin, and

gain setting ranges from +29.5 dB to – 97.5 dB when it is grounded through a capacitor.

LOUT

LOUT

LOUT

LOUT

––––

Left Channel Analog output

Lch analog output pin

Note this is an inverted output.

ROUT

ROUT

ROUT

ROUT

––––

Right Channel Analog output

Rch analog output pin

Note this is an inverted output.

VREF

VREF

VREF

VREF

––––

Analog Reference Voltage (output)

Analog reference voltage output pin

Outputs 1/2VDD. Ground through a capacitor of 10

µF or more to attain stabilization.

• Digital Pins

Digital Pins

Digital Pins

Digital Pins

SDATAI

SDATAI

SDATAI

SDATAI

––––

Serial Data Input

Serial data input pin

SDATAO

SDATAO

SDATAO

SDATAO

––––

Serial Data Output

Serial data putput pin

Outputs Serial data when CSN is “low”, or becomes high impedance state when it is “high”.

SCLK

SCLK

SCLK

SCLK

––––

Serial Clock (Input)

Serial clock input pin

CSN

CSN

CSN

CSN

––––

Chip Select (Input)

Chip select input pin

ICN

ICN

ICN

ICN

––––

DC Bias Initial Clear (Input)

DC bias initialization pin.

DC bias is set to VREF (analog reference voltage) when this is “low”.

To stabilize the bias voltage at power on, determine the control time in accordance with the coupling

capacitor that is connected to the inputs (LIN1, LIN2, RIN1 ,RIN2).

(Refer to “VREF stabilization time and DC bias initialization time” in the description of functions.)

ZCEN

ZCEN

ZCEN

ZCEN

––––

Zero Crossing Enable (Input)

Zero crossing control pin.

Making this pin “high” enables a mode where volume change is performed

after detecting zero crossing.

The volume change immediately after writing data when this pin is “low”.

TE

TE

TE

TE

––––

Test Enable (Input)

Test mode control pin.

Fix it to “low” or with NC when using.