continue to hold the ALERT pin low until it is allowed to

clear its own interrupt.

Clearing the interrupt has no effect on the state of the

status registers.

Input/Output Pins

Each IO_ pin is protected by an internal 20mA (typical)

current-limit circuit. Typical pulldown on-resistance at

Ω and 66Ω, respectively.

When the IO_ is high impedance, it actually has a

0.5µA pulldown current source included as part of the

read-back functionality.

External pullup resistors and IO_ sink capability can

affect the outputs’ rise and fall times. When using the

MAX1608/MAX1609 to control an external MOSFET in

power-switching applications, pullup and/or series resis-

tance can be used together with the MOSFET’s gate

capacitance or additional external capacitance (Figure 6)

to control the transition time of the switched source.

The input logic levels are TTL compatible and are sam-

pled during a readback SMBus transmission (see RSB

register in Data Registers section ).

Power-On Reset

The MAX1608/MAX1609s’ power-on-reset circuit

ensures that the IO_ states are defined when V+ is first

applied or when the supply dips below the UVLO

threshold. The power-on states can also be reset with

the SPOR command through the SMBus.

Octal SMBus-to-Parallel I/O Expanders

______________________________________________________________________________________

11

POR STATE

7

IO7

0

6

IO6

0

5

IO5

0

4

IO4

0

1

IO1

0

NAME

BIT

2

IO2

0

3

IO3

0

IO0

MAX1608

0

MAX1609

1

1

1

1

1

0

1

1

Sets IO1 state. 0 = on (low state), 1 = off (high-impedance).

Sets IO7 state. 0 = on (low state), 1 = off (high-impedance).

Sets IO6 state. 0 = on (low state), 1 = off (high-impedance).

Sets IO5 state. 0 = on (low state), 1 = off (high-impedance).

Sets IO4 state. 0 = on (low state), 1 = off (high-impedance).

Sets IO2 state. 0 = on (low state), 1 = off (high-impedance).

Sets IO3 state. 0 = on (low state), 1 = off (high-impedance).

FUNCTION

1

Sets IO0 state. 0 = on (low state), 1 = off (high-impedance).

Table 3. Data Register 1 (NDR1 and SDR1) Bit Assignments (Read or Write)

POR STATE

7

MASKH7

1

6

MASKH6

1

5

MASKH5

1

4

MASKH4

1

1

MASKH1

1

NAME

BIT

2

MASKH2

1

3

MASKH3

1

MASKH0

1

0

Masks IO1 low-to-high interrupt. 0 = interrupts, 1 = masked.

Masks IO7 low-to-high interrupt. 0 = interrupts, 1 = masked.

Masks IO6 low-to-high interrupt. 0 = interrupts, 1 = masked.

Masks IO5 low-to-high interrupt. 0 = interrupts, 1 = masked.

Masks IO4 low-to-high interrupt. 0 = interrupts, 1 = masked.

Masks IO2 low-to-high interrupt. 0 = interrupts, 1 = masked.

Masks IO3 low-to-high interrupt. 0 = interrupts, 1 = masked.

FUNCTION

Masks IO0 low-to-high interrupt. 0 = interrupts, 1 = masked.

Table 4. Data Register 2 (NDR2 and SDR2) Bit Assignments (Read or Write)