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AT90USB646 Datasheet(PDF) 308 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 308 Page - ATMEL Corporation |
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308 / 434 page  308 7593A–AVR–02/06 AT90USB64/128 Set by hardware when a transaction underflow occurs in the current isochronous or interrupt Pipe. The Pipe can’t send the data flow required by the device. A ZLP will be sent instead. An interrupt is triggered if the FLERRE bit is set. Shall be cleared by software. Setting by software has no effect. Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent and the UNDERFI bit is set underflow for interrupt Pipe: •4 - Reserved The value read from these bits is always 0. Do not set these bits. • 3-2 - DTSEQ1:0 - Toggle Sequencing Flag Set by hardware to indicate the PID data of the current bank: 00b Data0 01b Data1 1xb Reserved. For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the current bank. For IN Pipe, this value indicates the last data toggle received on the current bank. • 1-0 - NBUSYBK1:0 - Busy Bank Flag Set by hardware to indicate the number of busy bank. For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer. For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device. 00b All banks are free 01b 1 busy bank 10b 2 busy banks 11b Reserved. • 7-0 - INRQ7:0 - IN Request Number Before Freeze Enter the number of IN transactions before the USB controller freezes the pipe. The USB con- troller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed. Bit 7 654 321 0 INRQ7 INRQ6 INRQ5 INRQ4 INRQ3 INRQ2 INRQ1 INRQ0 UPINRQX Read/Write RW RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 43 21 0 - COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL UPERRX Read/Write RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0 |
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