AT90USB646 datasheet(311/434 Pages) ATMEL

311 / 434 page

311

7593A–AVR–02/06

AT90USB64/128

Set by hardware when a new USB message is stored in the current bank of the Pipe. This trig-

gers an interrupt if the RXINE bit is set in the UPIENX register.

Shall be cleared to handshake the interrupt. Setting by software has no effect.

• 7 - FLERRE - Flow Error Interrupt enable

Set to enable the OVERFI and UNDERFI interrupts.

Clear to disable the OVERFI and UNDERFI interrupts.

• 6 - NAKEDE -NAK Handshake Received Interrupt Enable

Set to enable the NAKEDI interrupt.

Clear to disable the NAKEDI interrupt.

•5 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 4 - PERRE -PIPE Error Interrupt Enable

Set to enable the PERRI interrupt.

Clear to disable the PERRI interrupt.

• 3 - TXSTPE - SETUP Bank ready Interrupt Enable

Set to enable the TXSTPI interrupt.

Clear to disable the TXSTPI interrupt.

• 2 - TXOUTE - OUT Bank ready Interrupt Enable

Set to enable the TXOUTI interrupt.

Clear to disable the TXOUTI interrupt.

• 1 - RXSTALLE - STALL Received Interrupt Enable

Set to enable the RXSTALLI interrupt.

Clear to disable the RXSTALLI interrupt.

• 0 - RXINE - IN Data received Interrupt Enable

Set to enable the RXINI interrupt.

Clear to disable the RXINI interrupt.

Bit

FLERRE

NAKEDE

PERRE

TXSTPE

TXOUTE

RXSTALLE

RXINE

UPIENX

Read/Write

Initial Value

Bit

654

321

PDAT7

PDAT6

PDAT5

PDAT4

PDAT3

PDAT2

PDAT1

PDAT0

UPDATX

Read/Write

Initial Value

AT90USB646 Datasheet(PDF) 311 Page - ATMEL Corporation

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