Z86L997 datasheet(21/102 Pages) ZILOG

21 / 102 page

Z86D990/Z86D991 OTP and Z86L99X ROM

Low-Voltage Microcontrollers with ADC

PS003807-1002

Figure 7. Z8 Expanded Register File Architecture

Clock Circuit Description

The Z8 derives its timing from on-board clock circuitry connected to pins XTAL1

and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping

circuit, and a clock buffer. The oscillator’s input is XTAL1, and the oscillator’s out-

put is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock,

RC, or an external clock source.

Clock Control

The Z8 offers software control of the internal system clock using programming

determines the mode of STOP Mode Recovery.

The default setting is external clock divide-by-two. When bits 1 and 0 of the SMR

to the external clock frequency divided by two.

When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the exter-

nal clock frequency. Refer to Table 53 on page 85 for the maximum clock fre-

quency.

A divide-by-16 prescaler of SCLK and TCLK allows the user to selectively reduce

device power consumption during normal processor execution (under SCLK con-

trol) and/or HALT mode, where TCLK sources counter/timers and interrupt logic.

Combining the divide-by-two circuitry with the divide-by-16 prescaler allows the

external clock to be divided by 32.

Z8 Standard Register File

Bank 0

Control and Status Reg.

I/O Port Registers

Working

Groups

Banks 2 through C are

Reserved—Not Implemented

Group 0, Bank D

Group 0, Bank F

(Bank E is also reserved)

General-Purpose

RAM Registers

Z8 Expanded Register Files

Timer

Control

Registers

Stop Mode

Recovery and

Port Mode

Bank F

Registers

Z86L997 Datasheet(PDF) 21 Page - Zilog, Inc.

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