ADE9153AACPZ datasheet(4/50 Pages) AD

4 / 50 page

ADE9153A

Data Sheet

Rev. 0 | Page 4 of 50

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC

PGA Gain Settings (xI_PGAGAIN)

Current Channel A (Phase Shunt)

16, 24,

32, 38.4

V/V

PGA gain setting is referred to as gain

Current Channel B (Neutral CT)

1, 2, 4

V/V

PGA gain setting is referred to as gain

Pseudo Differential Input Voltage

Range

(IAP − IAN)

−1/gain

+1/gain

44.19 mV rms on Current Channel A, AI_PGAGAIN = 16×

(VAP − VAN)

−0.5

+0.5

353.6 mV rms on voltage channel

Differential Input Voltage Range

(IBP − IBN)

−1/gain

+1/gain

707 mV rms on Current Channel B

Maximum Operating Voltage on

the Analog Input Pins

VAP

1.35

Voltage on the pin with respect to ground

IAP, IAN

−0.1125

+0.1125

Voltage on the IAx pin with respect to ground

IBP, IBN

0.35

1.45

Voltage on the IBx pin with respect to ground;

internal common-mode voltage at IBx pin = 0.9 V

SNR

Current Channel A

AI_PGAGAIN = 16×

VIN is a full-scale signal

AI_PGAGAIN = 38.4×

VIN is a full-scale signal

Current Channel B

BI_PGAGAIN = 1x

VIN is a full-scale signal

BI_PGAGAIN = 4x

VIN is a full-scale signal

Voltage Channel

VIN is a full-scale signal

ADC Output Pass Band (0.1 dB)

0.672

kHz

ADC Output Bandwidth (−3 dB)

1.6

kHz

Crosstalk

−120

At 50 Hz or 60 Hz; see the Terminology section

AC Power Supply Rejection Ratio

(AC PSRR)

At 50 Hz; see the Terminology section

Current Channel A

−115

Current Channel B

−100

Voltage Channel

−100

AC Common-Mode Rejection Ratio

(AC CMRR)

−120

At 50 Hz

ADC Gain Error

Percentage of error from the ideal value; see the

Terminology section

Current Channel A

±0.2

±1.5

Current Channel B

−2.0

±3.5

Voltage Channel

−0.8

±3.0

ADC Offset

Current Channel A

See the Terminology section

AI_PGAGAIN = 16×

+0.04

±0.1

AI_PGAGAIN = 38.4×

−0.02

±0.05

Current Channel B

−0.26

±0.37

Voltage Channel

+0.35

±0.75

ADC Offset Drift

±0.5

±5

μV/°C

See the Terminology section

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