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MAX5754 Datasheet(PDF) 21 Page - Maxim Integrated Products |
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MAX5754 Datasheet(HTML) 21 Page - Maxim Integrated Products |
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21 / 25 page ![]() 32-Channel, 14-Bit, Voltage-Output DACs with Serial Interface ______________________________________________________________________________________ 21 Read-Data Format The MAX5753/MAX5754/MAX5755 support daisy-chain connections of multiple devices. The default (power-up) configuration for the MAX5753/MAX5754/MAX5755 assumes that the device may be part of a daisy chain of devices. DOUT follows DIN after 32 clock cycles. For a read command, DOUT provides read data (instead of the data value shifted in) in the next cycle following a CS rising edge. Figures 5 and 6 show examples of daisy-chain data sequences. Shutdown Mode The MAX5753/MAX5754/MAX5755 feature a software- controlled low-power shutdown mode. When bit 9 of the configuration register is a logic high, the analog section of the device is disabled, and the outputs go high impedance. In shutdown, supply current is reduced to 50µA. Data stored in the DAC and input registers is retained, and the device outputs return to their previous values when the device is brought out of shutdown. The serial interface remains active while the device is in shutdown. Power-Up State The MAX5753/MAX5754/MAX5755 monitor the four power supplies and maintain the output buffers in a known state until sufficient voltage is available to ensure that no output glitches occur. Once the minimum voltage threshold has been passed, the device outputs come up in the clear state (all outputs = 0). For proper power sequencing, VSS must be applied first. Power sequencing is not necessary if VSS is connected to AGND. CONTROLLER DEVICE DIN DOUT 1 OR 0 SCLK CS MAX575_ DSP Figure 7. Stand-Alone Configuration CONTROLLER DEVICE DIN DOUT 1 OR 0 1 OR 0 1 OR 0 SCLK CS MAX575_ DIN DOUT SCLK CS MAX575_ DIN DOUT SCLK CS MAX575_ DSP DSP DSP Figure 8. Example of a Parallel Configuration with Read-Back C1 C2 C0 A5 A4 A3 A2 A1 A0 Sp Sp Sp Sp Sp Sp Sp D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 DIN(0) SCLK CS ( µC) CS (DSP) DOUT(0) OR Figure 9. Read Data Timing When Not Daisy-Chained |
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