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LTC4281 Datasheet(PDF) 3 Page - Analog Devices

Part # LTC4281
Description  High Voltage High Current Hot Swap Controller
PDF  32 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC4281 Datasheet(HTML) 3 Page - Analog Devices

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LTC4238
3
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
VDD
Input Supply Range
l
6.5
80
V
IDD
Input Supply Current
l
3
5
mA
VDD(UVLO)
Input Supply Undervoltage Lockout
VDD Rising
l
5.8
6
6.2
V
VDD(HYST)
Input Supply Undervoltage Lockout Hysteresis
l
500
mV
INTVCC
Internal 5V Supply Voltage
ILOAD = 0mA to 10mA
l
4.5
5.0
5.5
V
INTVCC(UVLO)
INTVCC Undervoltage Lockout Threshold
INTVCC Rising
l
3.75
4
4.25
V
INTVCC(HYST)
INTVCC Undervoltage Lockout Hysteresis
l
110
mV
Current Limit
ΔVSNS(TH)
Current Limit Sense Voltage Threshold
(SENSE+ – SENSE–)
ISET= 0V
ISET = INTVCC
l
l
5.8
19.5
6
20
6.2
20.5
mV
mV
10% Current Limit Foldback, Start-Up Only
ISET = 0V
ISET = INTVCC
l
l
0.18
1.6
0.6
2
0.9
2.4
mV
mV
30% Current Limit Foldback, Normal
VDD – VDSFB =12V
ISET = 0V
ISET = INTVCC
l
l
1.5
5.6
1.8
6
2.1
6.4
mV
mV
Current Limit Threshold DAC INL
l
0
±60
µV
ΔVSNS1 – ΔVSNS2 Current Limit Channel Voltage Mismatch
VSENSE1+, VSENSE2+ = 48V
l
0
±300
µV
αILIM(FAST)
Ratio of Fast Current Limit to Nominal ΔVSNS(TH)
l
2
3
4
ISENSE1+
SENSE1+ Input Current
VSENSE1+ = 48V, VSNS1 ≤ 20mV
l
0
150
µA
ISENSE1–
SENSE1– Input Current,
VSENSE1– = VSENSE2– = 48V
HSSS Mode with CH2 Off
l
3
5
7
µA
Parallel, LSSS Mode, HSSS Mode with
CH2 On
l
0
±1
µA
ISENSE2+
SENSE2+ Input Current
VSENSE2+ = 48V
l
0
70
µA
ISENSE2–
SENSE2– Input Current
VSENSE2+ = VSENSE2– = 48V
l
0
±1
µA
Gate Drive
ΔVGATE
External N-Channel Gate Drive (VGATE –VSOURCE) VDD = 6.5V to 80V, IGATE = –5μA (Note 3) l
10
12
14
V
ΔVGATE(TH)
Gate Threshold for FET-Bad and Power Good
l
6
8
10
V
IGATE(UP)
GATE1, GATE2 Pull-Up Current
Gate On, GATE = 0V
l
–35
–50
–70
µA
IGATE(DN)
GATE1, GATE2 Fast Pull-Down Current
ΔVSNS = 100mV, ΔVGATE = 6V
0.8
A
Gate Off Pull-Down Current to SOURCE
ΔVGATE = 6V
l
6
10
16
mA
Gate Off Pull-Down Current to Ground
ΔVGATE = 6V
l
0.5
1.5
2.5
mA
tPHL(SENSE)
ΔVSNS High to GATE Low Propagation Delay
ΔVSNS = 0mV to 100mV Step, C = 10nF
l
0.5
1
µs
tPHL(GATE)
UV, OV Turn Off Propagation Delay
GATE < 6V, Gate Open
l
0.3
1
3
µs
tPHL(STRESS)
Propagation Delay to Turn Off Low Stress
MOSFET in HSSS Mode
Gate Open
l
6
13
µs
Comparator Inputs
VTH
UV, OV, FB Threshold Voltage
Rising
l
2.5
2.56
2.62
V
ΔVUV(HYST)
UV Hysteresis
l
280
360
440
mV
ΔVOV(HYST)
OV Hysteresis
l
25
46
85
mV
ΔVFB(HYST)
FB Power Good Hysteresis
l
60
80
100
mV
VTH
UV Reset Threshold Voltage
Falling
l
0.95
1.00
1.05
V
ΔVUVR(HYST)
UV Reset Threshold Hysteresis
l
50
100
150
mV
IINPUT
UV, OV, FB Input Current
V = 2.56V
l
0
±1
μA



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