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MSM6653 Datasheet(PDF) 8 Page - OKI electronic componets

Part # MSM6653
Description  SI/SD Voice Recognizer, Recorder/Player, and Speech Synthesizer
PDF  46 Pages
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Manufacturer  OKI [OKI electronic componets]
Direct Link  http://www.oki.com
Logo OKI - OKI electronic componets

MSM6653 Datasheet(HTML) 8 Page - OKI electronic componets

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MSM6679AL-110 Voice Recognition Processor
¡ Semiconductor
6
PIN DESCRIPTIONS
Pin #
Pin Name Signal Type
Description
1
NC
(do not connect)
2
Reserved. These pins are reserved for future used and must be left open.
3
RESOUT
Output
MSM665x Reaet. This pin provides a reset signal for an external speech
synthesis engine.
4
STROBE
Output
MSM665x Strobe. This output provides the LOAD signal for an external
speech synthesizer.
5
BUSY
Input
MSM665x Busy. When using an external MSM665x device, this pin monitors
the MSM665x BUSY signal and connects directly to the MSM665x BUSY
signal output.
6
SI
Output
MSM665x Serial Clock. This MSM6679AL-110 output connects to the
MSM665x SI input. The SI pin is the MSM665x serial clock input pin.
7
SD
Output
MSM665x Serial Data. This MSM6679AL-110 output connects to the
MSM665x SD input. The SD pin is the MSM665x serial data input pin.
8
NC
(do not connect) Reserved. These pins are reserved for future use and must be left open.
9
10
VOICEOUT1
Output
Voice Out. This pin is the PWM output for speech synthesis, voice sample
playback, and voice prompts. An external integrator must be used to convert
this to an analog signal.
11
NC
(do not connect) Reserved. This pin is reserved for future use and must be left open.
12
NAR
Input
MSM665x Next Address Request. This pin signals to the MSM6679AL-110
that the external speech synthesis engine is ready for another command.
13
VDD
Digital Power Power.
14
GND
Digital Ground Ground.
15
NC
Input
Reserved. These pins are reserved for future use and must be tied to VDD.
16
17
18
NC
(do not connect) Reserved. This pin is reserved for future use and must be left open.
19
NC
Input
Reserved. This pin is reserved for future use and must be tied to VDD.
20
PDC
Input
Power down release. Power down mode is released by both edge of PDC
signal.



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