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ML60851C Datasheet(PDF) 21 Page - OKI electronic componets |
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ML60851C Datasheet(HTML) 21 Page - OKI electronic componets |
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21 / 67 page ![]() PEDL60851C-02 1Semiconductor ML60851C 21/67 Revision Register (REVISION) Read address CDh Write address — D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset After a bus reset Definition Revision No. of Chip Transmit FIFO Clear Register (CLRFIFO) Read address — Write address 4Eh D7 D6 D5 D4 D3 D2 D1 D0 After a hardware reset Cannot be read (indeterminate) After a bus reset Cannot be read (indeterminate) Definition 0 0 0 0 EP1 to EP3 FIFO Clear: When each EP has been set for transmission, by writing a “1” in these bits, the corresponding FIFOs are cleared at the Write pulse and also the corresponding EP Packet Ready bits are reset. EP1 Transmit FIFO Clear EP2 Transmit FIFO Clear EP3 Transmit FIFO Clear |
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