DLPA2000 datasheet(27/63 Pages) TI

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7.3.1.2 Parallel Interface

The parallel interface complies with standard graphics interface protocol, which includes the signals listed in

Table 7-2.

Table 7-2. Parallel Interface Signals

SIGNAL

DESCRIPTION

VSYNC_WE

vertical sync

HSYNC_CS

horizontal sync

DATAEN_CMD

data valid

PDATA

24-bit data bus

PCLK

pixel clock

PDM_CVS_TE

parallel data mask (optional)

Note

VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no

longer active, the display sequencer stops and causes the LEDs to turn off.

The active edge of both sync signals are variable. The Parallel Interface Frame Timing Requirements section

shows the relationship of these signals.

An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without

losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source

image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or

active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic

low signal. PDM_CVS_TE must only change during vertical blanking.

The parallel interface supports six data transfer formats. They are as follows:

• 24-bit RGB888 or 24-bit YCbCr888 on a 24 data wire interface

• 18-bit RGB666 or 18-bit YCbCr666 on an 18 data wire interface

• 16-bit YCbCr 4:2:2 (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, ...)

The Section 7.3.1.2.1 section shows the required PDATA(23:0) bus mapping for these six data transfer formats.

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DLPA2000 Datasheet(PDF) 27 Page - Texas Instruments