MPC5561 datasheet(2/58 Pages) NXP

2 / 58 page

MPC5561 Microcontroller Data Sheet, Rev. 3

Overview

Freescale Semiconductor

The MPC5500 family of parts contains many new features coupled with high performance CMOS

technology to provide significant performance improvement over the MPC565.

The host processor core of the MPC5561 also includes an instruction set enhancement allowing variable

length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this

enhancement, it is possible to significantly reduce the code size footprint.

The MPC5561 has two levels of memory hierarchy. The fastest accesses are to the 32-kilobytes (KB)

unified cache. The next level in the hierarchy contains the 192-KB on-chip internal SRAM and one

megabyte (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data.

The external bus interface is designed to support most of the standard memories used with the MPC5xx

family.

The less complex timer functions of the MPC5561 are performed by the enhanced modular input/output

system (eMIOS). The eMIOS’ 24 hardware channels are capable of single-action, double-action,

pulse-width modulation (PWM), and modulus-counter operations. Motor control capabilities include

edge-aligned and center-aligned PWM.

Off-chip communication is performed by a suite of serial protocols including controller area networks

(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPIs), and enhanced serial communications

interfaces (eSCIs).

The Parallel Digital Interface (PDI) block provides a glueless interface from the MPC5500 family of

devices to high speed external parallel devices such as Analog to Digital Convertors (ADCs) and image

sensors. The PDI module, with its internal Direct Memory Access (DMA) engine, moves external parallel

data into system memory with minimum intervention from the host processor. The host processor can also

read data from the PDI via an interrupt directly.

The MCU has an on-chip enhanced queued dual analog-to-digital converter (eQADC).324 s 40-channels.

The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration

and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset

control are also determined by the SIU. The internal multiplexer submodule provides multiplexing of

eQADC trigger sources and external interrupt signal multiplexing.

The FlexRay controller provides functional node networking, with static and dynamic host access, to

develop highly dependable automotive control systems that require the full implementation of the FlexRay

protocol, as published in FlexRay Protocol Specification 2.0. The FlexRay module uses fault-tolerant,

time-triggered events and clock synchronization mechanisms to maintain the global time of the functional

nodes. Bus guardian operations are available for each channel in a multi- or redundant-channel

configuration.

MPC5561 Datasheet(PDF) 2 Page - NXP Semiconductors