MPC5561 datasheet(49/58 Pages) NXP

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Revision History for the MPC5561 Data Sheet

MPC5561 Microcontroller Data Sheet, Rev. 3

Freescale

5.3

Information Changed Between Revisions 0.0 and 1.0

The following table lists the global changes made throughout the document, as well as substantive changes

to text that is not in a table of figure.

Table 24 (eMIOS Timing) eMIOS Timing:

• Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’

• Deleted (MTS) from the heading, table, and footnotes.

• Footnote 1: Deleted ‘. . .fSYS = 132 MHz. . .’, ‘. . .VDD33 and VDDSYN = 3.0–3.6 V. . .’ and ‘ . . .and CL = 200 pF

with SRC = 0b11.’

• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum

eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad

configuration registers (PCR).’

Table 25 (DSPI Timing’) DSPI Timing:

• Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’

• Table Title: Added footnote that reads: Speed is the nominal maximum frequency. Max. speed is the maximum

speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM;

114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts allow for 132 MHz system clock +

2% FM.

Table 26 (EQADC SSI Timing Characteristics) EQADC SSI Timing Characteristics:

• Footnote 1, changed ‘VDDEH = 4.5–5.5;’ to ‘VDDEH = 4.5–5.25;’

• Deleted from table title ‘(Pads at 3.3 V or 5.0 V)’

• Deleted 1st line in table ‘CLOAD = 25 pF on all outputs. Pad drive strength set to maximum.’

• Spec 1: FCK frequency -- removed.

• Combined footnotes 1 and 2, and moved the new footnote to Spec 2. Moved old footnote 3 to Spec 2.

• Footnote 1, deleted ‘VDD = 1.35–1.65 V’ and ‘VDD33 and VDDSYN = 3.0–3.6V.’

Changed ‘CL = 50 pF’ to ‘CL = 25 pF.’

• Footnote 2: added ‘cycle’ after ‘duty’ to read: FCK duty cycle is not 50% when . . . .

Figure 27 (MPC5561 324 Package) MPC5561 324 PBGA Pinouts:

• Changed ball labels on the 324 PBGA to show only signals available on the device:

• C1 -> PSCS3, C2 -> PCSC4,

• D1 -> PCSC1, D2 -> PCSC2, D3 -> IRQ14

• E1 -> IRQ12, E2 -> IRQ15, E3 -> IRQ13, E4 -> IRQ9

• F1 -> IRQ11, F2 -> IRQ10, F3 -> PDI_DATA6, F4 -> PDI_DATA7

• G1 -> IRQ8, G2 -> PDI_DATA8, G3 -> PCSB4, G4 -> PCSB3

• H1 -> PDI_DATA5, H2 -> PCSB5, H3 -> PDICHSEL2

• J1 -> PCSB1, J2 -> PDI_DATA0, J3 -> FRN_RX, J4 -> PDICHSEL1

• K1 -> PDICHSEL0, K2 -> GPIO121, K3 -> PDI_FRAME_VALID, K4 -> FRBTXEN, K19 -> RXDD

• L1 -> FRBTX, L2 -> PDISNCLK, L3 -> GPIO114, L4 -> PDILINEVALID, L20 -> PCSC5, L21 -> PCSC2,

L22 -> PCSC1

• M2 -> IRQ7, M19 -> PCSB2, M20 -> TXDC, M21 -> TXDD

• N19 -> RXDC, N21 -> PCSB3

• AB18 -> PCSC3, AB19 -> PCSC4

Table 28. Information Changed Between Rev. 1.0 and Rev. 2.0 (continued)

Location

Description of Changes

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