PEDL7048-01-01

1Semiconductor

ML7048-01

13/20

TIMING DIAGRAM

Note: In the above diagram, 3-channel independent serial interface is selected.

When 3-channel continuous serial interface is selected, 24-bit data is output from DOUT1 in the

order of Channel 1, Channel 2, and Channel 3.

Figure 1 Transmit side Timing Diagram

Note: In the above diagram, 3-channel independent serial interface is selected.

When 3-channel continuous serial interface is selected, 24-bit data is input to DIN1 in the order of

Channel 1, Channel 2, and Channel 3.

Figure 2 Receive Side Timing Diagram

Note: DOUT and AOUT will not rise before inputting XSYNC.

Figure 3 SGC, DOUT, AOUT Outputs Timing

BCLK

XSYNC

DOUTn

T

XS

D2

1

2345678

T

SX

T

XD1

T

SD

D3

D4

D5

D6

D7

D8

MSD

T

WS

T

XD2

T

RS

D2

1

2345678

T

SR

T

DS

T

WS

T

DH

D3

D4

D5

MSD

D6

D7

D8

BCLK

RSYNC

DINn

PDN

T

SGC

SGC

PDNn

T

DDO

DOUTn

T

DAO

SG Level

High Impedance

AOUTn±