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MMPF0200Z Datasheet(PDF) 66 Page - NXP Semiconductors |
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MMPF0200Z Datasheet(HTML) 66 Page - NXP Semiconductors |
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66 / 118 page  Analog Integrated Circuit Device Data 66 Freescale Semiconductor PF0200Z Functional Block Requirements and Behaviors Power Generation 6.4.6 LDO Regulators Description This section describes the LDO regulators provided by the PF0200Z. All regulators use the main bandgap as reference. Refer to Bias and References Block Description section for further information on the internal reference voltages. A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest bias currents may be attained by forcing the part into its Low Power mode by setting the VGENxLPWR bit. The use of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low. Figure 19. General LDO Block Diagram VGENx VINx VINx VGENx CGENx VGENxEN VGENxLPWR VREF VGENx I 2C Interface Discharge + _ |
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