OPA2191 datasheet(34/59 Pages) TI

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9.2.2.2 Detailed Design Procedure

The purpose of this application example is to design an optimal, high-voltage, multiplexed, data-acquisition

system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 9-4.

The circuit is a multichannel, data-acquisition, signal chain consisting of an input low-pass filter, multiplexer

(mux), mux output buffer, attenuating SAR ADC driver, digital counter for the mux, and the reference driver. The

architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two

primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system

are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,

carefully design each analog circuit block based on the ADC performance specifications in order to achieve

the fastest settling at 16-bit resolution and lowest distortion system. Figure 9-4 includes the most important

specifications for each individual analog block.

This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input

stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the

design is to understand the requirement for an extremely-low-impedance input-filter design for the mux. This

understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system

settling requirements. The next important step is the design of the attenuating analog front-end (AFE) used to

level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability.

Then, the next step is to design a digital interface to switch the mux input channels with minimum delay. The final

design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference

voltage with low offset, drift, and noise contributions.

9.2.3 Slew Rate Limit for Input Protection

In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.

By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and

down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one

additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high

output current and slew rate of the OPAx191 make the device an optimal amplifier to achieve slew rate control

for both dual-supply and single-supply systems. Figure 9-5 shows the OPA191 in a slew-rate limit design. For

step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results,

refer to TI Precision Design TIPD140, Single Op-Amp Slew Rate Limiter..

VCC

VEE

VOUT

VIN

Op Amp Gain Stage

Slew Rate Limiter

OPA191

VCC

VEE

OPA191

Figure 9-5. Slew Rate Limiter Uses One Op Amp

OPA191, OPA2191, OPA4191

SBOS701D – DECEMBER 2015 – REVISED AUGUST 2021

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