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ADIN2111BCPZ-R7 Datasheet(PDF) 16 Page - Analog Devices |
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ADIN2111BCPZ-R7 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 125 page  Data Sheet ADIN2111 THEORY OF OPERATION analog.com Rev. 0 | 16 of 125 Table 14. Determination of Master/Slave by Autonegotiation Local1 Remote1 Local Remote AN_ADV_FORCE_MS AN_ADV_MST AN_LP_ADV_FORCE_MS AN_LP_ADV_MST Master/Slave Resolution 0 0 0 0 Master/slave Slave/master 0 0 0 1 Slave Master 0 1 0 0 Master Slave 0 1 0 1 Master/slave Slave/master 0 X 1 0 Master Slave 0 X 1 1 Slave Master 1 0 0 X Slave Master 1 1 0 X Master Slave 1 0 1 0 Configuration fault Configuration fault 1 0 1 1 Slave Master 1 1 1 0 Master Slave 1 1 1 1 Configuration fault Configuration fault 1 X means don't care. Autonegotiation Fail On a 10BASE-T1L link, autonegotiation can fail due to the following scenarios: ► Configuration fault, such as invalid master/slave configuration ► Link quality issues ► Timeout in pages transmission If autonegotiation fails, it restarts. The link remains down until the autonegotiation process completes. MDI The ADIN2111 provides a two-pin MDI for each port (Port 1 and Port 2) with internal termination resistors and an internal hybrid, to connect the ADIN2111 ports to the Ethernet network via a twisted wire pair. The two ports are connected to the internal PHYs (PHY 1 and PHY 2). SPI The ADIN2111 can be interfaced to the host controller via the four-pin SPI, allowing frame transfer and control of the internal switch MAC registers and the internal PHYs core management registers via the SPI to MDIO bridge. The interface is compatible with both IEEE Standard 802.3 Clause 22 and Clause 45 management frame structures (see the Register Summary: 10BASE-T1L Single Pair Ethernet PHY Core (ADIN2111) section). The SPI is compatible with the OPEN Alliance SPI protocol and supports a generic SPI mode. The SPI operating mode is set using the SPI_CFG0 and SPI_CFG1 hardware configuration pin signals (see the Hardware Configuration Pins section). HARDWARE INTERRUPT (INT) The ADIN2111 can generate a hardware interrupt to a host control- ler using the INT pin. This pin can be configured to trigger interrupts from the following sources: ► PHY 1/PHY 2 status ► PHY 1/PHY 2 data ready ► PHY 1/PHY 2 system errors ► Frame and overflow errors ► IEEE 1588 timestamp capture ► Reset interrupt ► Software requested interrupt Switch Subsystem Interrupt When an interrupt occurs, the system can poll the Status Register 0 (STATUS0) and the Status Register 1 (STATUS1) to determine the origin of the interrupt. The switch subsystem interrupts can be configured to trigger the INT pin using the Interrupt Mask Register 0 (IMASK0) and the mask bits for driving the interrupt pin register (IMASK1). PHY Subsystem Interrupts The following conditions can be selected to generate an interrupt on each of the ADIN2111 PHYs: ► MAC interface frame checker/generator interrupt ► MAC interface buffers overflow/underflow interrupt ► Autonegotiation status change interrupt ► Link status change interrupt |
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