...........continued

Name

Symbol

Buffer Type

Description

Bias Resistor

RBIAS

AIO

External bias resistor connection pin. This pin requires

connection of a 12.4 kΩ resistor to ground.

Note:  The resistor must be within ± 1% tolerance across the

entire expected operating temperature range.

Do Not Connect

DNC

-

Pin is internally connected. The pin must be left floating

externally.

No Connect

NC

-

Pin is not connected internally. The pin should be left floating

externally.

Table 3-8. Configuration Straps

Name

Symbol

Buffer Type

Description

Operating Mode Configuration

Straps 1-0

MODE[1:0]

VIS-VDDP

These configuration straps are used to select the device’s

default mode of operation. See Section 3.5, Configuration

Straps for additional information.

PHY Address Configuration

Straps 4-0

PHYAD[4:0]

VIS-VDDP

These configuration straps are used to select the device’s

default PHY SMI address. See Section 3.5, Configuration

Straps for additional information.

Table 3-9. Power Pins

Name

Symbol

Buffer Type

Description

+3.3V Switched I/O Power Supply

Input

VDDP

P

+3.3V switched I/O power supply input.

+3.3V Switched Analog Power

Supply Input

VDDA

P

+3.3V switched analog power supply input.

Ground

VSS

P

Common ground.

This exposed pad must be connected to the ground plane with

a via array.

3.5

Configuration Straps

Configuration straps allow various features of the device to be automatically configured to user defined values.

Configuration straps are identified by an underlined symbol name in the pin assignment lists and are latched on

Power-On Reset (POR) and pin reset (RESET_N). Configuration straps do not have internal resistors to prevent the

signal from floating when unconnected.

Important:  External pull-up or pull-down resistors must be sized appropriately (10 kΩ, typical) to ensure

that the configuration straps reach the required voltage level prior to latching at reset.

3.5.1

Device Mode (MODE[1:0])

The MODE[1:0] configuration straps control various device modes. When the RESET_N pin is negated, the

associated register bit values are loaded according to the MODE[1:0] configuration straps and the device is

configured. When a soft reset occurs via the Soft Reset bit of the Basic Control Register, the configuration of the

device is controlled by the register bit values and the MODE[1:0] configuration straps have no affect.

The device’s mode may be configured using the hardware configuration straps as summarized in Table 3-10 below.

Note:  As the LAN8672 only supports operation in MII mode, the MODE[1:0] configuration straps must be set to 01b.

LAN8670/1/2

Pin Description and Configuration

and its subsidiaries

Product Brief

DS60001536E-page 14