ISO6760LDWR datasheet(21/44 Pages) TI

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8.3 Feature Description

Table 8-1 provides an overview of the device features.

Table 8-1. Device Features

PART NUMBER

CHANNEL DIRECTION

MAXIMUM DATA

RATE

OUTPUT

PACKAGE

RATED ISOLATION(1)

ISO6760L

6 Forward,

3 Interlock Pairs

50 Mbps

Non-Inverted

DW-16

5000 VRMS / 7000 VPK

ISO6760LN

6 Forward,

3 Interlock Pairs

50 Mbps

Inverted

DW-16

5000 VRMS / 7000 VPK

(1)

See for detailed isolation ratings.

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO676x

family of devices incorporates many chip-level design improvements for overall system robustness. Some of

these improvements include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

8.3.2 Interlock Capability

The ISO6760L family incorporates a series of logic gates to protect adjacent channel pairings from both

registering high simultaneously. When paired with an IPM, this interlock circuitry provides protection proventing

shoot through current to both the high-side and low-side switch of the module. This design, shown in ISO6760L

Channel Pairing Block Diagram of Interlock, is used to make sure that when one of the channel pairings is logic

high, the other channel will output logic low. ISO6760L Device Truth Table provides the logic output state to the

corresponding input state for ISO6760L and ISO6760LN (Inverted) Device Truth Table provides the logic output

state to the corresponding input state for ISO6760LN (inverted output version).

INx_L

OUTx_L

INx_H

OUTx_H

Figure 8-3. ISO6760L Channel Pairing Block Diagram of Interlock

ISO6760L Device Truth Table

INx_H

INx_L

OUTx_H

OUTx_L

High

Low

High

Low

High

Low

High

Low

Floating

Low

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ISO6760L

SLLSFO3 – DECEMBER 2021

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