LTC3886 datasheet(21/26 Pages) AD

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LTC7883

Rev. 0

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APPLICATIONS INFORMATION

Table 7. ASELn Resistor Programming

RTOP (kΩ) RBOT (kΩ)

ASEL1

ASEL0

LTC3882-1 DEVICE

ADDRESS BITS[6:4]

LTC3882-1 DEVICE

ADDRESS BITS[3:0]

BINARY

HEX

BINARY

HEX

0 or Open

Open

from EEPROM

23.2

1111

15.8

1110

16.2

20.5

1101

16.2

17.4

1100

17.8

1011

1010

12.7

1001

1000

24.9

11.3

111

0111

24.9

9.09

110

0110

24.9

7.32

101

0101

24.9

5.76

100

0100

24.9

4.32

011

0011

30.1

3.57

010

0010

30.1

1.96

001

0001

Open

000

0000

Design Example

As a design example, consider a 180W 4-phase applica-

tion such as the one shown in Figure 1, where VIN = 12V,

VOUT = 1.5V, and IOUT = 120A. An auxiliary 7V source

supplies the LTC7883 VCC pins and the power stage FET

gate drive voltage with a 2.2µF ceramic bypass, in addi-

tion to a smaller 0.1µF ceramic placed near the LTC7883

filtering HF components. Bypassing is also provided for

each VDD33 (2.2µF) and VDD25 (1µF) LDO output. These

LDO outputs should not be shared with each other or

separate ICs that might have outputs of the same name,

because they have independent, internal control loops.

The Delta D12S1R8140D power block is chosen for its

high level of integration, power efficiency and direct

interface to the LTC7883 using 3.3V three-state control.

The use of a power block with the LTC7883 creates an

efficient solution in terms of power, parts count and total

solution volume. Placing the power stage directly beneath

the LTC7883 on the other side of the PCB allows direct

through-hole via connections to the power block for PWM

controls, as well as output voltage and current sense.

Table 8 shows the recommended channel mapping for

the most efficient interconnect in this case. CCM opera-

tion, fast boost refresh, low VOUT range and digital output

voltage servo are selected by programming MFR_PWM_

MODE_LTC3882-1 to 0xC0 on all channels.

Table 8. Suggested Power Block Channel Mapping

LTC7883 PWM

LTC7883 UNIT

PMBus PAGE

(CH)

PB PWM

The regulated output is established by programming the

VOUT_COMMAND stored in EEPROM for PWMA0 (the

master channel) to 1.5V. The other PWMs are designated

as slaves to PWMA0 by wiring their FB pins to VDD33 and

shorting their COMP control pins to COMPA0 as shown.

The frequency and phase are also set by EEPROM val-

ues. Both units are programmed to operate at 500kHz

(default FREQUENCY_SWITCH), with Unit A providing

the clock master (see Figure 3, SYNCB output disabled

by bit 4 of MFR_CONFIG_ALL_LTC3882-1 on Unit B).

MFR_PWM_CONFIG_LTC3882-1 is programmed to 0x14

on Unit A to put PWMA0 phase at 0° and PWMA1 phase

at 180°. This register is programmed to 0x16 on Unit B

to put PWMB0 phase at 90° and PWMB1 phase at 270°,

producing optimum 4-phase separation for minimum

input and output ripple.

With these configurations, the inductors on the

power block (160nH nominal) create an IOUT ripple of

16.4AP-P. Each channel supplies 40ADC to the output at

full load, resulting in a peak phase current of 48A. Setting

IOUT_FAULT_LIMIT to 50A per phase adequately protects

against the typical inductor saturation current of 55A.

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