EM78468Q datasheet(21/71 Pages) EMC

21 / 71 page

EM78468

8-BIT Microcontroller

Product Specification (V1.1) 04.11.2005

• 17

(This specification is subject to change without further notice)

CPU Operation Mode

Green Mode

fm:stop

fs:oscillation

CPU: usingfs

Normal Mode

fm:oscillation

fs:oscillation

CPU: usingfosc

IDLE Mode

fm:stop

fs:oscillation

CPU: stop

SLEEP Mode

Fm:stop

Fs: stop

CPU: stop

IDLE="1"

SLEP

IDLE="0"

SLEP

wakeup

Wake up

RESET

CPUS="1"

CPUS="0"

Code option

HLFS=0

Code option

HLFS=1

The w ake up time from idle to green

mode is 16*1/fs

The w ake up time from sleep to green mode is

approximately sub-oscillator setup time +18ms+16*1/fs

it must delay a little times for the main

oscillation stable w hile your system timing

control is conscientious

Fig. 5 CPU Operation Mode

4.1.15 RE/IRCR (IR and PORT 5 Setting Control Register)

(Address: 0Eh)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IRE

LGP

IROUTE

TCCE

EINT1

EINT0

Bit 7 (IRE): Infrared Remote Enable bit

IRE = “0”: Disable IR/PWM function. The state of P5.7/IROUT pin is determined

by bit 7 of IOC50 if it’s for IROUT.

IRE = “1”: Enable IR or PWM function.

Bit 6 (HF): High carry frequency.

HF = “0”: For PWM application, disable H/W modulator function. IROUT

waveform is created according to high-pulse and low-pulse time as determined by

the high pulse and low pulse width timers respectively. The counter 2 is an

independent auto reload timer.

HF = “1”: For IR application mode, enable H/W modulator function, the low time

sections of the generated pulse is modulated with the frequency Fcarrier. The

frequency of Fcarrier provide by counter 2.

Bit 5 (LGP): IROUT for long time of low pulse.

LGP = “0”: The high-pulse width timer register and low-pulse width timer is valid.

LGP = “1”: The high-pulse width timer register is ignored. So the IROUT

waveform is dependent on low-pulse width timer register only.

Bit 4: Not used

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