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MM54HC533 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # MM54HC533
Description  TRI-STATE-R Octal D-Type Latch with Inverted Outputs
PDF  4 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

MM54HC533 Datasheet(HTML) 3 Page - National Semiconductor (TI)

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AC Electrical Characteristics VCCe5V TAe25 C tretfe6ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
tPHL tPLH
Maximum Propagation Delay Data to Q
CLe45 pF
18
25
ns
tPHL tPLH
Maximum Propagation Delay Enable to Q
CLe45 pF
21
30
ns
tPZH tPZL
Maximum Output Enable Time
RLe1kX
20
28
ns
CLe45 pF
tPHZ tPLZ
Maximum Output Disable Time
RLe1kX
18
25
ns
CLe5pF
tS
Minimum Set Up Time
5
ns
tH
Minimum Hold Time
10
ns
tW
Minimum Pulse Width
16
ns
AC Electrical Characteristics VCCe20V–60V CLe50 pF tretfe6 ns (unless otherwise specified)
TAe25 C
74HC
54HC
Symbol
Parameter
Conditions
VCC
TAeb40 to 85 CTAeb55 to 125 C
Units
Typ
Guaranteed Limits
tPHL tPLH
Maximum Propagation
CLe50 pF
20V
50
150
188
225
ns
Delay Data to Q
CLe150 pF
20V
80
200
250
300
ns
CLe50 pF
45V
22
30
37
45
ns
CLe150 pF
45V
30
40
50
60
ns
CLe50 pF
60V
19
26
31
39
ns
CLe150 pF
60V
26
35
44
53
ns
tPHL tPLH
Maximum Propagation
CLe50 pF
20V
63
175
220
263
ns
Delay Enable to Q
CLe150 pF
20V
110
225
280
338
ns
CLe50 pF
45V
25
35
44
52
ns
CLe150 pF
45V
35
45
56
68
ns
CLe50 pF
60V
21
30
37
45
ns
CLe150 pF
60V
28
39
49
59
ns
tPZH tPZL
Maximum Output Enable Time
RLe1kX
CLe50 pF
20V
50
150
188
225
ns
CLe150 pF
20V
80
200
250
300
ns
CLe50 pF
45V
21
30
37
45
ns
CLe150 pF
45V
30
40
50
60
ns
CLe50 pF
60V
19
26
31
39
ns
CLe150 pF
60V
26
35
44
53
ns
tPHZ tPLZ
Maximum Output Disable Time
RLe1kX
20V
50
150
188
225
ns
CLe50 pF
45V
21
30
37
45
ns
60V
19
26
31
39
ns
tS
Minimum Set Up Time
20V
50
60
75
ns
45V
9
13
15
ns
60V
9
11
13
ns
tH
Minimum Hold Time
20V
5
5
5
ns
45V
5
5
5
ns
60V
5
5
5
ns
tW
Minimum Pulse Width
20V
30
80
100
120
ns
45V
10
16
20
24
ns
60V
9
14
18
20
ns
tTHL tTLH
Maximum Output Rise
CLe50 pF
20V
25
60
75
90
ns
and Fall Time Clock
45V
7
12
15
18
ns
60V
6
10
13
15
ns
CPD
Power Dissipation Capacitance
(per latch)
(Note 5)
OCeVCC
30
pF
OCeGnd
50
pF
CIN
Maximum Input Capacitance
5
10
10
10
pF
COUT
Maximum Output Capacitance
15
20
20
20
pF
Note 5
CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3



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