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MM54HC533 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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MM54HC533 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 4 page  TLF5339 January 1988 MM54HC533MM74HC533 TRI-STATE Octal D-Type Latch with Inverted Outputs General Description These high speed OCTAL D-TYPE LATCHES utilize ad- vanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of stan- dard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads Due to the large output drive capability and the TRI-STATE feature these devices are ideally suited for interfacing with bus lines in a bus organized system When the LATCH ENABLE input is high the data present on the D inputs will appear inverted at the Q outputs When the LATCH ENABLE goes low the inverted data will be re- tained at the Q outputs until LATCH ENABLE returns high again When a high logic level is applied to the OUTPUT CONTROL input all outputs go to a high impedance state regardless of what signals are present at the other inputs and the state of the storage elements The 54HC74HC logic family is speed function and pin-out compatible with the standard 54LS74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Typical propagation delay 18 ns Y Wide operating voltage range 2 to 6 volts Y Low input current 1 mA maximum Y Low quiescent current 80 mA maximum (74HC Series) Y Compatible with bus-oriented systems Y Output drive capability 15 LS-TTL loads Connection Diagram Dual-In-Line Package TLF5339 – 1 Top View Order Number MM54HC533 or MM74HC533 Truth Table Latch Output Enable Control G Data Output LH H L LH L H LL X Q0 HX X Z H e high level L e low level Q0 e level of output before steady-state input conditions were established Z e high impedance TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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