9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output

Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected

directly together. This can cause excessive current and damage to the device.

Two channels within the same device with the same input signals can be connected in parallel for additional

output drive strength.

Refer to Feature Description section for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure

optimal performance. This can be accomplished by providing short, appropriately sized traces from the

SN74HCS151-Q1 to one or more of the receiving devices.

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in MΩ; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

CBA

G

Y

b000

b010

b001

b000

D0

D1

D2

Figure 9-2. Application timing diagram

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps

to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The

bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the

following layout example.

11 Layout

11.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many

cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a

triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left

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SCLS819B – AUGUST 2020 – REVISED DECEMBER 2021

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