AD7657BSTZ datasheet(23/25 Pages) AD

23 / 25 page

Preliminary Technical Data

AD7658/AD7657/AD7656

Rev. PrI | Page 23 of 25

Standby/Partial Power Down Modes of Operation

Each ADC pair can be individually placed into partial power

down by bringing the CONVSTX signal low before the falling

edge of BUSY. To power the ADC pair back up again then the

CONVSTX signal should be brought high to tell the ADC pair

to power up and place the track-and-hold into track mode. In

partial power down mode the reference buffers will remain

powered up. While an ADC pair is in partial power down,

conversions can still occur on the other ADCs.

The AD7658/AD7657/AD7656 has a standby mode whereby

the device can be placed into a low current consumption mode

(0.5 µA max). The AD7658/AD7657/AD7656 is placed into

standby mode by bringing the logic input STBY low. The

AD7658/AD7657/AD7656 can be powered up again for normal

operation by bringing STBY logic high. The output data buffers

are still operational when the AD7658/AD7657/AD7656 is in

standby. This means the user can still continue to access the

conversion results when the AD7658/AD7657/AD7656 is in

standby. This standby feature can be used to reduce the average

power consumed by the AD7658/AD7657/AD7656 when

operating at lower throughput rates. The

AD7658/AD7657/AD7656 could be placed into standby at the

end of each conversion when BUSY goes low and taken out of

standby again prior to the next conversion. The time it takes for

the AD7658/AD7657/AD7656 to come out of standby is called

the “wake-up” time. This wake-up time will limit the maximum

throughput rate at which the AD7658/AD7657/AD7656 can

operate when powering down between conversions.

AD7657BSTZ Datasheet(PDF) 23 Page - Analog Devices