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USB4715 Datasheet(PDF) 36 Page - Microchip Technology |
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USB4715 Datasheet(HTML) 36 Page - Microchip Technology |
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36 / 47 page ![]() USB4715 DS00002514B-page 36 2022 Microchip Technology Inc. and its subsidiaries 9.6.8 SPI/SQI TIMING This section specifies the SPI/SQI timing requirements for the device. FIGURE 9-5: SPI/SQI TIMING TABLE 9-7: SPI/SQI TIMING (30 MHZ OPERATION) Symbol Description Min Typ Max Units tfc Clock frequency 30 MHz tceh Chip enable ( SPI_CE_N/SQI_CE_N) high time 100 ns tclq Clock to input data 13 ns tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable ( SPI_CE_N/SQI_CE_N) low to first clock 12 ns tceh Last clock to chip enable ( SPI_CE_N/SQI_CE_N) high 12 ns TABLE 9-8: SPI/SQI TIMING (60 MHZ OPERATION) Symbol Description Min Typ Max Units tfc Clock frequency 60 MHz tceh Chip enable ( SPI_CE_N/SQI_CE_N) high time 50 ns tclq Clock to input data 9 ns tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable ( SPI_CE_N/SQI_CE_N) low to first clock 12 ns tceh Last clock to chip enable ( SPI_CE_N/SQI_CE_N) high 12 ns SPI_CLK/ SQI_CLK SPI_DI/ SQI_D[3:0] (in) SPI_DO/ SQI_D[3:0] (out) SPI_CE_N/ SQI_CE_N tcel tfc Output data valid tclq tceh tdh toh tos tov toh Output data valid Input data valid tceh |
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