MAX11259 datasheet(21/51 Pages) MAXIM

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If data was read, then RDYB transitions from high to low at the output data rate. If the previous data was not read, then

the RDYB transitions from low to high for four master clock cycles and then transitions from high to low. In continuous

mode, RDYB remains high for the first four conversion results and on the 5th result, RDYB goes low.

For sequencer mode 2 and sequencer mode 3, the RDYB behavior for a multichannel conversion can be controlled

by the SEQ:RDYBEN bit. The default value of SEQ:RDYBEN is ‘0’. When set to ‘0’, RDYB behaves the same for

multichannel conversion and single channel operation. The RDYB toggles high to low after each channel is ready to

update its corresponding data register. After the channel data is read, the RDYB will reset back to ‘1’. If the channel

data is not read and the next channel is ready to update its data, the RDYB will toggle low to high four cycles before the

data update (similar to a single channel operation), and then toggle high to low indicating the new channel’s conversion

data is available. If ‘N’ channels are enabled, RDYB will toggle high to low ‘N’ times. If SEQ:RDYBEN is set to ‘1’, the

RDYB event for each channel is suppressed. The RDYB toggles high to low when the last channel is ready to update its

corresponding data register and a single high to low transition happens.

The STAT:SRDY[5:0] bits get set to ‘1’ when their corresponding channel finishes converting, irrespective of the

RDYBEN setting for sequencer modes 2 and 3. The conversion status is available by reading the STAT:MSTAT bit. This

stays high as long as the modulator is converting.

See Figure 4 for timing of RDYB.

SDA (Serial Data Input/Output)

The SDA line is considered an input when the master is transmitting the data to the MAX11259. The SDA line will be

used as an output when the MAX11259 has data to be sent onto the I2C bus during a register read by the host master.

The slave in the MAX11259 implements mandatory requirements as specified in I2C standard, which are detections of

START and STOP conditions and support for ACK/NACK. This slave supports 7-bit addressing and does not support the

general call address.

I2C Sequence:

The master needs to send out the first byte with a valid device address. The last bit of the first byte is a R/W bit and

the master needs to send a '0' in this bit. The device will ignore a '1' sent in this bit. This is followed by a COMMAND

BYTE for the MAX11259 as described in the command structure. The MAX11259 then responds to the command request

depending on the MODE bit in the command.

Writing a Command to the MAX11259 for Conversion/ Calibration/Power-Down

1. I2C START

2. I2C WRITE

a. Send Device Address with a '0' in bit 8 indicating the master will send a command byte followed by the device

address. (8’b0110000_0)

b. Check Acknowledge

c. Send Command byte to convert/power down/calibrate (8’b10_01_xxxx)

d. Check acknowledge

3. I2C STOP

MAX11259

24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA, Delta-

Sigma ADC with I2C Interface

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MAX11259 Datasheet(PDF) 21 Page - Maxim Integrated Products