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MAX11259 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX11259 Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 51 page ![]() Electrical Characteristics (VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V to 3.6V, VREFP - VREFN = VAVDD, DATA RATE = 1ksps, PGA low-noise mode, single- cycle conversion mode (SCYCLE = 1). TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)(Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Single-Cycle Conversion Mode) Noise Voltage (Referred to Input) Vn PGA gain of 128, single-cycle mode at 1ksps data rate PGA low-noise mode 0.19 µVRMS PGA low-power mode 0.26 PGA gain of 128, single-cycle mode at 12.8ksps data rate PGA low-noise mode 0.83 PGA low-power mode 1.16 Integral Nonlinearity INL 3 15 ppm Zero Error ZERR After system zero-scale calibration 1 µV Zero Drift ZDrift 50 nV/°C Full-Scale Error FSE After system full-scale calibration (Notes 4 and 5) 2 ppmFSR Full-Scale Error Drift FSEDrift 0.05 ppm FSR/°C Common-Mode Rejection CMR DC rejection 110 130 dB 50Hz/60Hz rejection (Note 6) 110 130 DC rejection with PGA gain 64 80 105 DC rejection with PGA gain 128 95 AVDD, AVSS Supply Rejection Ratio PSRRA DC rejection 73 95 dB 50Hz/60Hz rejection (Note 6) 75 95 DC rejection with PGA gain 128 65 75 DVDD Supply Rejection Ratio PSRRD DC rejection 105 115 dB 50Hz/60Hz rejection (Note 6) 105 115 DC rejection with PGA gain 128 90 110 PGA Gain Setting 1 128 V/V Noise-Spectral Density NSD Low-noise mode 6.2 nV/√Hz Low-power mode 10 Gain Error, Not Calibrated GERR Gain = 1 0.75 % Gain = 2 1.2 Gain = 4 2 Gain = 8 3 Gain = 16 4.5 Gain = 32 6 Gain = 64 5.5 Gain = 128 2 Output Voltage Range VOUTRNG VAVSS + 0.3 VAVDD - 0.3 V MAX11259 24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA, Delta- Sigma ADC with I2C Interface www.analog.com Analog Devices | 4 |
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