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MAXAUDINT1 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAXAUDINT1 Datasheet(HTML) 5 Page - Maxim Integrated Products |
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5 / 22 page ![]() Maxim Integrated │ 5 www.maximintegrated.com Evaluates: MAXAUDINT1 Audio Interface 1 appears as a sound card to the PC and shows up as a USB Audio playback device in Windows’ Sound dialog. Configure the USB Audio device as the default playback device (by pressing Set Default) to have audio from the PC streamed onto the AUDINT1 board. When audio is being streamed onto the AUDINT1 board, LEDB (located to the left of the XMOS device) turns on. In order for the audio stream to be routed onto the con- nected DEV board, the I2S switch needs to be configured in the CONNECTED position (Table 5). Note: The PCM digital audio signals are routed through a level-translator/buffer (U5 and U7) and a switch (U3) before routing to the J1 connector. *Default position. X = Don’t care MCLK SWITCH MSEL SWITCH CLOCK SOURCE DISCONNECTED X On-board clock is not provided to DEV board. Use this setting if the DEV board does not require a master clock or if an external master clock is used. Connect the external master clock to pin 2 of header J3 or pin 1 of connector J1. CONNECTED* SEL The on-board clock selected by the evaluation software (11.2896MHz, 12MHz, or 12.288MHz). CONNECTED 12MHz On-board 12MHz oscillator *Default position. SWITCH ACTUATOR POSITION DESCRIPTION I2C DISCONNECT Disconnects the I2C interface from the J1 connector CONNECT* Connects the I2C interface to the J1 connector I2S DISCONNECT Disconnects the I2S interface from the J1 connector CONNECT* Connects the I2S interface to the J1 connector MCLK DISCONNECT Disconnects the MCLK clock output from the J1 connector CONNECT* Connects the MCLK clock output to the J1 connector MSEL SEL* Master clock output connected to one of the three on-board clocks (11.2896MHz, 12MHz, 12.288MHz). 12MHz Master clock output connected to the on-board 12MHz oscillator SW1 DEMO Interface board evaluated in demonstration mode EVAL* Interface board evaluated in evaluation mode HEADER SHUNT POSITION DESCRIPTION DVDD +1.2V Provides +1.2V to the digital logic rail on the J1 connector (pin 13) +1.8V* Provides +1.8V to the digital logic rail on the J1 connector (pin 13) +3.3V Provides +3.3V to the digital logic rail on the J1 connector (pin 13) GND Grounds the digital logic rail on the J1 connector (pin 13) VIO +1.8V* Provides +1.8V to the I/O logic rail on the J1 connector (pin 15) +3.3V Provides +3.3V to the I/O logic rail on the J1 connector (pin 15) *Default position. Table 6. Master Clock Configuration Table 5. Switch Configuration Table 4. Jumper Configuration |
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