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SPC584B70E5 Datasheet(PDF) 1 Page - STMicroelectronics |
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SPC584B70E5 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 142 page  This is information on a product in full production. September 2019 DS11701 Rev 4 1/142 SPC584Bx 32-bit Power Architecture microcontroller for automotive ASIL-B applications Datasheet - production data Features AEC-Q100 qualified High performance e200z420 – 32-bit Power Architecture technology CPU – Core frequency as high as 120 MHz – Variable Length Encoding (VLE) 2112 KB (2048 KB code flash + 64 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation 176 KB HSM dedicated flash memory (144 KB code + 32 KB data) 128 KB on-chip general-purpose SRAM (in addition to 64 KB core local data RAM Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Multi-channel direct memory access controller (eDMA) with 64 channels 1 interrupt controller (INTC) Comprehensive new generation ASIL-B safety concept – ASIL-B of ISO 26262 – FCCU for collection and reaction to failure notifications – Memory Error Management Unit (MEMU) for collection and reporting of error events in memories – Cyclic redundancy check (CRC) unit Enhanced low power support – Ultra low power STANDBY – Smart Wake-up Unit – Fast wake-up and execute from RAM Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution Body cross triggering unit (BCTU) – Triggers ADC conversions from any eMIOS channel – Triggers ADC conversions from up to 2 dedicated PIT_RTIs Enhanced analog-to-digital converter system with: – 2 independent fast 12-bit SAR analog converters – 1 supervisor 12-bit SAR analog converter – 1 10-bit SAR analog converter with STDBY mode support Communication interfaces – 1 Ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008 – 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support – 14 LINFlexD modules – 7 Deserial Serial Peripheral Interface (DSPI) modules Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus Development Interface (NDI) per IEEE- ISTO 5001-2003 standard, with some support for 2010 standard eTQFP100 (14 x 14 x 1.0 mm) eTQFP64 (10 x 10 x 1.0 mm) eTQFP144 (20 x 20 x 1.0 mm) eTQFP176 (24 x 24 x 1.4 mm) www.st.com |
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