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TLV9352IDDFR Datasheet(PDF) 31 Page - Texas Instruments |
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TLV9352IDDFR Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 63 page ![]() 10.2 Layout Example + VIN VOUT RG RF Figure 10-1. Schematic Representation NC ±IN +IN V± V+ OUTPUT NC NC VS+ VS± GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible RF RG Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor GND Use a low-ESR, ceramic bypass capacitor Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration V- OUT GND GND GND Figure 10-3. Example Layout for SC70 (DCK) Package www.ti.com TLV9351, TLV9352, TLV9354 SBOS994E – NOVEMBER 2019 – REVISED JANUARY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TLV9351 TLV9352 TLV9354 |
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