MPC8535E datasheet(96/127 Pages) NXP

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MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7

Electrical Characteristics

Freescale Semiconductor

This figure shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. Since LVPECL

driver’s DC levels (both common mode voltages and output swing) are incompatible with chip’s SerDes reference clock input’s

DC requirement, AC-coupling has to be used. This figure assumes that the LVPECL clock driver’s output impedance is 50

Ω.

R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140

Ω to 240Ω depending on

clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

Ω termination resistor to

attenuate the LVPECL output’s differential peak level such that it meets the chip’s SerDes reference clock’s differential input

amplitude requirement (between 200mV and 800mV differential peak). For example, if the LVPECL output’s differential peak

is 900mV and the desired SerDes reference clock input amplitude is selected as 600mV, the attenuation factor is 0.67, which

requires R2 = 25

Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with

a particular clock driver chip.

Figure 64. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC

levels of the clock driver are compatible with chip’s SerDes reference clock input’s DC requirement.

Figure 65. Single-Ended Connection (Reference Only)

SDn_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

10nF

10 nF

SDn_REF_CLK

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

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