MAX11284 datasheet(21/44 Pages) MAXIM

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Power-On Reset

The ADCs contain power-on reset (POR) supply-

monitoring circuitry on both the digital supply (DVDD) and

the positive analog supply (AVDD). The POR circuitry

ensures proper device default conditions after either a

digital or analog power-sequencing event.

The digital POR trigger threshold is typically 1.2V with

respect to VDGND and has 100mV of hysteresis. The

analog POR trigger threshold is typically 1.25V with

respect to VAVSS and has 100mV of hysteresis. Both

POR circuits have low-pass filters that prevent high-

frequency supply glitches from triggering the POR.

Power-Down Modes

The ADCs can be powered down through the IMPD bit in

the command byte (see Table 10). The PD[1:0] bits of the

CTRL1 register are used to select the power-down state.

The SPI interface remains fully functional in all power-

down states.

Sleep Mode: Sleep mode can be set by writing 01 to the

PD[1:0] bits. In this state, the internal subregulator that

powers the digital core is powered off. This is the lowest

power state for the device.

Standby Mode: Standby mode is set by writing 10 to the

PD[1:0] bits. In this mode the device is not active, but

the internal subregulator is still powered on. This allows

conversions to start immediately after receiving a start

conversion command (see Table 10).

*VIN = 0V. VAVDD = 3.6V, VAVSS = 0V, VREF = 3.6V, TA = +25°C, external clock. This table is not production tested and is based on

characterization data.

Table 6. Continuous Mode Input-Referred Noise (µVRMS) vs.

Data Rate and PGA Gain with Sinc Filter*

DATA

RATE

(sps)

BYPASS BUFFER

PGA GAIN SETTING

128

0.4875

0.283

0.270

0.307 0.251 0.127 0.137 0.066 0.071 0.032 0.042 0.019 0.023 0.011 0.015 0.011 0.011 0.008 0.012

0.975

0.271

0.280

0.261 0.259 0.139 0.139 0.066 0.070 0.035 0.042 0.022 0.025 0.013 0.015 0.010 0.012 0.008 0.012

1.95

0.328

0.288

0.265 0.290 0.140 0.148 0.074 0.084 0.043 0.046 0.024 0.024 0.015 0.017 0.011 0.015 0.011 0.016

3.9

0.342

0.339

0.332 0.346 0.168 0.182 0.092 0.094 0.047 0.053 0.029 0.031 0.018 0.023 0.014 0.020 0.013 0.020

7.8

0.429

0.435

0.416 0.415 0.213 0.227 0.112 0.117 0.060 0.062 0.036 0.039 0.024 0.030 0.018 0.027 0.018 0.026

15.625

0.539

0.563

0.528 0.532 0.268 0.264 0.140 0.145 0.072 0.079 0.046 0.053 0.031 0.041 0.026 0.038 0.024 0.036

31.25

0.696

0.724

0.669 0.723 0.354 0.359 0.179 0.189 0.097 0.106 0.059 0.072 0.042 0.057 0.034 0.053 0.033 0.051

62.5

0.930

0.961

0.928 0.940 0.472 0.479 0.248 0.258 0.135 0.146 0.082 0.097 0.056 0.081 0.049 0.074 0.047 0.074

125

1.266

1.299

1.258 1.301 0.657 0.660 0.349 0.349 0.191 0.204 0.120 0.145 0.094 0.125 0.086 0.115 0.083 0.112

250

1.751

1.777

1.754 1.767 0.917 0.911 0.476 0.483 0.268 0.292 0.172 0.201 0.132 0.172 0.088 0.159 0.114 0.163

500

2.475

2.430

2.440 2.460 1.236 1.260 0.672 0.663 0.363 0.392 0.227 0.276 0.181 0.229 0.118 0.222 0.154 0.213

1,000

3.323

3.320

3.304 3.348 1.712 1.727 0.872 0.877 0.481 0.511 0.306 0.355 0.227 0.305 0.151 0.286 0.197 0.279

2,000

4.160

4.189

4.193 4.307 2.160 2.161 1.121 1.105 0.603 0.645 0.373 0.454 0.285 0.378 0.183 0.356 0.236 0.345

4,000

4.716

4.694 4.769 2.381 2.431 1.210 1.214 0.688 0.729 0.404 0.499 0.333 0.409 0.211 0.408 0.253 0.381

8,000

6.700

6.612

6.688 6.650 3.513 3.451 1.754 1.811 0.974 1.056 0.604 0.709 0.441 0.586 0.288 0.560 0.352 0.541

16,000

10.010

10.256 10.038 10.395 5.154 5.157 2.603 2.635 1.428 1.566 0.880 1.048 0.585 0.842 0.406 0.761 0.482 0.751

MAX11284

Dual 24-Bit, Low-Power, High-SNR,

4ksps Delta-Sigma ADCs with Integrated PGAs

www.maximintegrated.com

Maxim Integrated │ 21

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