Integrated

Circuit

Systems, Inc.

874005AG

www.icst.com/products/hiperclocks.html

REV. A JANUARY 25, 2006

8

ICS874005

Figure 5 shows an example of ICS874005 application sche-

matic. In this example, the device is operated at V

R3

100

R1

10

C8

.1uf

R2

100

+

-

+

-

F_SELB

BW_SEL

CLK

C7

.1uf

F_SELA

MR

C6

.1uf

C3

10uF

C4

0.01u

OEA

(U1:4)

U1

874005_tssop24

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

nQB2

nQA1

QA1

VDDO

QA0

nQAO

MR

BW_SEL

VDDA

F_SELA

VDD

OEA

CLK

nCLK

GND

GND

OEB

F_SELB

nQB0

QB0

nQB1

QB1

VDDO

QB2

R5

50

VDDO = 3.3V

Zo = 50 Ohm

OEB

Zo = 50 Ohm

Zo = 50 Ohm

(U1:23)

Zo = 50 Ohm

Zo = 50 Ohm

C5

10uf

nCLK

R6

50

LVPECL Driv er

R4

50

(U1:11)

Zo = 50 Ohm

VDD = 3.3V

decoupling capacitor should be located as close as possible

to the power pin. The input is driven by a 3.3V LVPECL driver.

A general LVDS interface is shown in Figure 4. In a 100

Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100

Ω across near

100 Ohm Differiential Transmission Line

R1

100

3.3V

+

-

LVDS_Driv er

3.3V

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.