| Electronic Components Datasheet Search |
|
ADA4254ARUZ-R7 Datasheet(PDF) 54 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADA4254ARUZ-R7 Datasheet(HTML) 54 Page - Analog Devices |
|
54 / 59 page ![]() ADA4254 Data Sheet Rev. B | Page 54 of 59 ERROR CONFIGURATION REGISTER Table 27. CFG_C Register Details (Register 0x0D) Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ERR_LATCH_DIS Reserved ERR_DELAY[3:0] Access RW Reserved RW RW RW RW Reset 0 Reserved 0 1 0 0 Bit 7, ERR_LATCH_DIS—Disable Error Latching By default, ERR_LATCH_DIS is cleared to 0 and error flags are latched and require resetting. Setting ERR_LATCH_DIS to 1 makes the errors appear transparently (nonlatching) on the respective outputs. When ERR_LATCH_DIS is set to 1, errors can be suppressed for the time interval configured by ERR_DELAY. Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time When ERR_LATCH_DIS is set to 1, ERR_DELAY determines the number of clock cycles an error must remain present before the error flag is tripped, which eliminates false trips due to noise and transients. Table 28. Error Flag Suppression Time ERR_DELAY[3:0] Clock Cycles (μS) 0x0 0 0x1 1 0x2 2 0x3 3 0x4 4 0x5 5 0x6 6 0x7 7 0x8 8 0x9 12 0xA 16 0xB 24 0xC 32 0xD 48 0xE 64 0xF 127 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |