ADE7978 datasheet(77/125 Pages) AD

77 / 125 page

Data Sheet

ADE7978/ADE7933/ADE7932/ADE7923

Rev. D | Page 77 of 125

SIGN OF SUM OF PHASE POWERS IN THE CFx

DATAPATH

The ADE7978 has sign detection circuitry for the sum of phase

powers that are used in the CFx datapath. As described in the

Energy-to-Frequency Conversion Process section, the energy

accumulation in the CFx datapath is executed in two stages. Each

time a sign change is detected in the energy accumulation at the

end of the first stage—that is, after the energy accumulated in the

accumulator reaches one of the WTHR, VARTHR, or VATHR

thresholds—a dedicated interrupt can be triggered synchronously

with the corresponding CFx pulse. The sign of each sum can be

read in the PHSIGN register (Address 0xE617).

Bit 18, Bit 13, and Bit 9 (REVPSUM3, REVPSUM2, and

REVPSUM1, respectively) of the STATUS0 register are set to 1

when a sign change of the sum of powers in the CF3, CF2, or CF1

datapaths occurs. To correlate these events with the pulses gener-

ated at the CFx pins after a sign change occurs, the REVPSUM3,

REVPSUM2, or REVPSUM1 bit is set when a high to low

transition occurs at the CF3, CF2, or CF1 pin, respectively.

Bit 8, Bit 7, and Bit 3 (SUM3SIGN, SUM2SIGN, and

SUM1SIGN, respectively) of the PHSIGN register are set to 1 when

the REVPSUM3, REVPSUM2, and REVPSUM1 bits are set to 1.

The SUMxSIGN bits indicate the sign of the sum of phase powers.

When these bits are cleared to 0, the sum is positive. When the

bits are set to 1, the sum is negative.

Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,

REVPSUM2, and REVPSUM1, respectively) in the STATUS0

MASK0 register. If enabled, the IRQ0 pin is set low and the

status bit is set to 1 when a change of sign occurs. To identify

the phase that triggered the interrupt, read the PHSIGN register

immediately after reading the STATUS0 register. Then clear the

status bit by writing a 1 to the appropriate bit in the STATUS0

ADE7978 Datasheet(PDF) 77 Page - Analog Devices