Internal-Switch Boost Regulator and High-Voltage,

Low-Dropout Linear Regulator for TFT LCDs

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Step-Up Regulator

The largest portions of power dissipation in the step-

up regulator are the internal MOSFET, the inductor,

and the output diode. If the step-up regulator has 90%

efficiency, approximately 3% to 5% of the power is lost

in the internal MOSFET, approximately 3% to 4% in the

inductor, and approximately 1% in the output diode.

The remaining 1% to 3% is distributed among the input

and output capacitors and the PCB traces. If the input

power is approximately 5W, the power loss in the internal

MOSFET is approximately 150mW to 250mW. The follow-

ing formula can be used to estimate the power loss in

the internal power MOSFET (excluding switching losses):

2

LX_ON

IN(DC,MAX)

DSON

P

I

R

D

=

×

×

MOSFET.

Operational Amplifiers

The power dissipated in the buffer amplifier depends on

the output current, the output voltage, and the supply

voltage:

(

)

SOURCE

OPO_SOURCE

VOP

OPO

PD

= I

V

- V

×

SINK

OPO_SINK

OPO

PD

= I

V

×

the amplifier sinks.

High-Voltage LDO Regulator

The power dissipation of the high-voltage LDO depends

on load current and the voltage drop between VREF_I and

VREF_O. It can be estimated by the following formula:

LR LOAD

DROP

P =I

V

×

PCB Layout and Grounding

Careful PCB layout is important for proper operation. Use

the following guidelines for good PCB layout:

U

Minimize the area of high-current loops by placing

the inductor, the output diode, and the output capaci-

tors near the input capacitors and near the LX and

PGND pins. The high-current input loop goes from the

positive terminal of the input capacitor to the induc-

tor, to the IC’s LX pin, out of PGND, and to the input

capacitor’s negative terminal. The high-current output

loop is from the positive terminal of the input capaci-

tor to the inductor, to the output diode (D1), and to the

positive terminal of the output capacitors, reconnect-

ing between the output capacitor and input capacitor

ground terminals. Connect these loop components

with short, wide connections. Avoid using vias in the

high-current paths. If vias are unavoidable, use many

vias in parallel to reduce resistance and inductance.

Create a power-ground island (PGND) consisting

of the input and output capacitor grounds, PGND

pin, and any charge-pump components. Connect

all these together with short, wide traces or a small

ground plane. Maximizing the width of the power

ground traces improves efficiency and reduces out-

put voltage ripple and noise spikes. Create an analog

ground plane (AGND) consisting of the AGND pin, all

the feedback-divider ground connections, the opera-

tional amplifier divider ground connection, the COMP,

VDPM and SS capacitor ground connections, and the

device’s exposed backside pad. Connect the AGND

and PGND islands by connecting the PGND pin

directly to the exposed backside pad. Make no other

connections between these separate ground planes.

U

Place all feedback voltage-divider resistors within

5mm of their respective feedback pins. The divider’s

center trace should be kept short. Placing the resis-

tors far away causes their FB traces to become

antennas that can pick up switching noise. Take care

to avoid running any feedback trace near LX or the

switching nodes in the charge pumps, or provide a

ground shield.

U

Place the IN pin bypass capacitors as close as pos-

sible to the device. The ground connection of the IN

bypass capacitor should be connected directly to the

AGND pin with a wide trace.

U

Minimize the length and maximize the width of the

traces between the output capacitors and the load for

best transient response.

U

Minimize the size of the LX node while keeping it wide

and short. Keep the LX node away from feedback

nodes (FB) and analog ground. Use DC traces to

shield necessary.

Refer to the MAX17115 evaluation kit for an example of

proper PCB layout.